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| 型號： | AD9992BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9992
Rev. C | Page 32 of 92
XV1
XV8
HD
XV9
XV10
XV1 TO XV8 USE
V-PATTERN GROUP A
XV9, XV10 USE
V-PATTERN GROUP B
05
89
1-
03
6
Figure 36. Using Separate Group A and Group B V-Patterns
XV1
XV24
HD
V-PATTERN GROUP A
V-PATTERN GROUP B
V-PATTERN GROUP C
V-PATTERN GROUP D
05
89
1-
0
37
Figure 37. Combining Multiple V-Patterns Using CONCAT_GRP = 1
XV1
XV10
HD
V-PATTERN GROUP A V-PATTERN GROUP B
GROUP A REP 1
GROUP A REP 2
GROUP A REP 3
05
89
1-
0
38
Figure 38. Combining Group A and Group B V-Patterns with Repetition
Group A/Group B/Group C/Group D Selection
The AD9992 has the flexibility to use four different V-pattern
groups in a vertical sequence. In general, the vertical outputs
use the same V-pattern group during a particular sequence. It is
possible to assign some of the outputs to a different V-pattern
group, which can be useful in certain CCD readout modes.
The GROUPSEL registers are used to select Group A, Group B,
Group C, or Group D for each V-output. In general, only a single
V-pattern group is needed for the vertical outputs; therefore,
Group A should be selected for all outputs by default
(GROUPSEL_0, GROUPSEL_1 = 0x00). In this configuration,
all outputs use the V-pattern group specified by the VPATSELA
register.
If additional flexibility is needed, some outputs can be set to
Group B, Group C, or Group D in the GROUPSEL registers.
In this case, those selected outputs use the V-pattern group
specified by the VPATSELB, VPATSELC, or VPATSELD
registers. Figure 36 shows an example where outputs XV9 and
XV10 are using a separate V-Pattern Group B to perform
special CCD timing.
Another application of the Group A, Group B, Group C, and
Group D registers is to combine up to four different V-pattern
groups together for more complex patterns. This is accom-
plished by setting the CONCAT_GRP register (Address 0x00,
Bits [13:10]) equal to 0x01. This setting combines the toggle
positions from the V-pattern groups specified by the VPATSELA,
VPATSELB, VPATSELC, and VPATSELD registers for a maximum
of up to 16 toggle positions. Example timing for the CONCAT_
GRP = 1 feature is shown in Figure 37.
If only two groups are needed (up to eight toggle positions) for
the specified timing, the VPATSELB, VPATSELC, and
VPATSELD registers can be programmed to the same value.
If only three groups are needed, VPATSELC and VPATSELD
can be programmed to the same value. Following this approach
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500 |
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