- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1895 > AD9992BBCZRL (Analog Devices Inc)IC CCD SGNL PROC 12BIT 105CSPBGA PDF資料下載
參數(shù)資料
| 型號： | AD9992BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 62/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁當(dāng)前第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
AD9992
Rev. C | Page 65 of 92
Table 26. Power-Up Register Write Sequence
Address
Data
Description
0x10
0x01
Resets all registers to default values
0x26
User-defined
Standby3 vertical output polarities
0x20 to
0xFFF
User-defined
Horizontal, vertical, shutter timing
0xD8
0x888
Configures start-up register
0x00
0x04
Powers up the AFE, enables OB clamp
0x15
0x01
Starts CLO oscillator (if using crystal)
0x14
0x01
Starts internal timing core
0x20
0x01
Configures for master mode
0x11
0x01
Enables all outputs after SYNC
0x13
0x4XX1
SWSYNC (if using software SYNC)
Using the SWSYNC Register
If an external SYNC pulse is not available, it is possible to
generate an internal SYNC in the AD9992 by writing 1 to the
SWSYNC register (Address 0x13, Bit 14). If the software SYNC
option is used, the SYNC input (Pin D3) should be low (VSS)
during power-up. The SYNCENABLE register (Address 0x13,
Bit 0) should be set high.
SYNC During Master Mode Operation
The hardware SYNC input can be used anytime during
operation to synchronize the AD9992 counters with external
timing, as shown in Figure 75. The operation of the digital
outputs can be suspended during the SYNC operation by set-
ting the SYNCSUSPEND register (Address 0x13, Bit 2) to 1. If
SYNCSUSPEND = 1, the polarities of the outputs are held at the
same state as OUTCONTROL = low, as shown in Table 27.
Power-Up and Synchronization in Slave Mode
The power-up procedure for slave mode operation is the same
as the procedure for master mode operation with two exceptions:
Eliminate Step 8. Do not write the part into master mode.
No SYNC pulse is required in slave mode. Substitute
Step 10 with starting the external VD and HD signals.
This synchronizes the part, allows the register updates,
and starts the timing operation.
When the AD9992 is used in slave mode, the VD/HD inputs are
used to synchronize the internal counters. After a falling edge of
VD, there is a latency of 36 master clock CLI edges after the falling
edge of HD until the internal H-counter is reset. The reset
operation is shown in Figure 76.
Additional Restrictions in Slave Mode
When operating in slave mode, the following restrictions
should be noted:
The HD falling edge should be located in the same CLI
clock cycle as the VD falling edge or later than the VD
falling edge. The HD falling edge should not be located
within five cycles prior to the VD falling edge.
If possible, all start-up serial writes should be performed
with VD and HD disabled. This prevents unknown
behavior caused by partial updating of registers before all
information is loaded.
VD
HD
SUSPEND
SYNC
H1 TO H4, RG,
XV1 TO XV24,
VSG, SUBCK
NOTES
1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x13).
4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW.
5. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL THE SYNC RESET EDGE.
05
89
1-
0
70
Figure 75. SYNC Timing to Synchronize the AD9992 with External Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9995KCPZ | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| ADA4424-6ARUZ | IC FILTR VID6CH SD/ED/HD 38TSSOP |
| ADATE302-02BBCZ | IC DCL ATE 500MHZ DUAL 84CSPBGA |
| ADATE304BBCZ | IC DCL ATE 200MHZ DUAL 84CSPBGA |
| ADATE305BSVZ | IC DCL ATE 250MHZ DUAL 100TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9994BCP | 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 12-BIT 64LFCSP - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。