參數(shù)資料
型號： AD9992BBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 79/92頁
文件大?。?/td> 0K
描述： IC CCD SGNL PROC 12BIT 105CSPBGA
產(chǎn)品變化通告： AD9992 Discontinuation 22/Feb/2012
標準包裝： 2,000
類型： CCD 信號處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 27mA
安裝類型： 表面貼裝
封裝/外殼： 105-LFBGA，CSPBGA
供應商設備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9992
Rev. C | Page 80 of 92
Address
Data Bits
Default
Value
Update
Type
Mnemonic
Description
[13:6]
0
MANUAL_TRIG
1: Manual trigger for GP signals, when Protocol 1 is
selected.
Bit 6: GP1 manual trigger.
…
Bit 13: GP8 manual trigger.
0x71
[12:0]
0
VD
PRIMARY_MAX
Primary counter maximum value.
[24:13]
0
SECOND_MAX
Secondary counter maximum value.
[27:25]
0
VDHD_MASK
Mask VD/HD during counter operation.
0x72
[12:0]
0
VD
PRIMARY_DELAY
Number of fields to delay before the next count
(exposure) starts.
ShotTimer with RapidShot, skip delay before first count
(exposure).
[13]
0
PRIMARY_SKIP
Number of fields to delay before the next count starts.
ShotTimer with RapidShot, skip delay before first count.
[26:14]
0
SECOND_DELAY
[27]
0
SECOND_SKIP
0x73
[2:0]
0
VD
GP1_PROTOCOL
Selects protocol for each general-purpose signal.
[5:3]
0
GP2_PROTOCOL
Idle = 0.
[8:6]
0
GP3_PROTOCOL
No counter association = 1.
[11:9]
0
GP4_PROTOCOL
Link to primary = 2.
[14:12]
0
GP5_PROTOCOL
Link to secondary = 3.
[17:15]
0
GP6_PROTOCOL
Link to mode = 4.
[20:18]
0
GP7_PROTOCOL
Primary repeat = 5.
[23:21]
0
GP8_PROTOCOL
Secondary repeat = 6.
Keep on = 7.
0x74
[12:0]
0
VD
SGMASK_NUM
Exposure: number of fields to mask SGs.
[25:13]
0
SUBCKMASK_NUM
Exposure plus readout: number of fields to mask SUBCK.
[26]
1
SUBCKTOG_UPDATE
0: SUBCK toggles (Register 0x77) updated on SG line.
1: SUBCK toggles (Register 0x77) updated on UPDATE line
(VD-updated).
[27]
0
SUBCKMASK_SKIP1
Skip the SUBCK mask for the first exposure field only.
Typically set to 1.
0x75
[0]
0
SG
TEST
Reserved for test purpose. Must be set to 0.
[13:1]
0
SUBCKSTARTLINE
Line location after VSG line to begin SUBCK pulses.
Must not be set to 1.
[26:14]
0
SUBCKNUM
Number of SUBCK pulses per field. Must be set less than
VDLEN.
[27]
0
SG_SUPPRESS
Suppress the SG and allow SUBCK to finish at
SUBCKNUM.
0x76
[12:0]
1FFF
VD
SUBCK_TOG1
SUBCK Toggle Position 1.
[25:13]
1FFF
SUBCK_TOG2
SUBCK Toggle Position 2.
[26]
0
SUBCK_POL
SUBCK start polarity.
0x77
[12:0]
1FFF
VD/SG
SUBCKHP_TOG1
High precision SUBCK Toggle Position 1.
[25:13]
1FFF
SUBCKHP_TOG2
High precision SUBCK Toggle Position 2.
0x78
[0]
0
VD
GP1_POL
GP1 low/high start polarity.
[1]
0
GP2_POL
GP2 low/high start polarity.
[2]
0
GP3_POL
GP3 low/high start polarity.
[3]
0
GP4_POL
GP4 low/high start polarity.
[4]
0
GP5_POL
GP5 low/high start polarity.
[5]
0
GP6_POL
GP6 low/high start polarity.
[6]
0
GP7_POL
GP7 low/high start polarity.
[7]
0
GP8_POL
GP8 low/high start polarity.
[8]
1
SEL_GP1
1: GP1 signal is selected for GPO1 output.
[9]
1
SEL_GP2
1: GP2 signal is selected for GPO2 output.
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