
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 5: The Clock Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
5-34
3.2 Registers Description
Table 11: CLOCK MODULE REGISTERS
Bit
Symbol
Acces
s
Value
Description
PLL Registers
Offset 0x04,7000
PLL0_CTL
Reset values set for expected frequencies for faster boot-up, shorter boot code.
31:30
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
29
Turn Off Acknowledge
R
-
Indicates that during a frequency change that the clock has been
driven low.
28
PLL Lock
R
-
A ‘1’ indicates that the PLL is locked
27:24
pll0_adj
R/W
0
23:21
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
20:12
pll0_n
R/W
0x4A
9-bit N parameter to PLL0
11:10
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
9:4
pll0_m
R/W
0x5
3:2
pll0_p
R/W
0
1
pll0_pd
R/W
0
1: powerdown PLL0
0
pll0_bp
R/W
1
0: Do not bypass the DDS
1: Bypass the DDS and use the xtal (27 MHz). Normal Operating
mode.
Offset 0x04,7004
PLL1_CTL
Reset values set for expected frequencies for faster boot-up, shorter boot code.
31:30
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
29
Turn Off Acknowledge
R
-
Indicates that during a frequency change that the clock has been
driven low.
28
PLL Lock
R
-
A ‘1’ indicates that the PLL is locked
27:24
pll1_adj
R/W
4
23:21
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
20:12
pll1_n
R/W
0x22
11:10
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
9:4
pll1_m
R/W
6
3:2
pll1_p
R/W
2
1
pll1_pd
R/W
0
1: powerdown PLL1
0
pll1_bp
R/W
1
0: Do not bypass the DDS.
1: Bypass the DDS and use the xtal (27 MHz)