
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
7-41
2
clr_dma_r_mabort
R
0
Clear DMA Received Master Abort
1
clr_dma_r_tabor
R
0
Clear DMA Received Target Abort
0
Reserved
R
0
Offset 0x04 0FDC
DMA Interrupt Set
31:15
Reserved
R
0
14
set_dma_xio_ack_done
R
0
Set Rising edge of xio_ack has been observed
13
Reserved
R
0
12
set_dma_done
R
0
Set DMA transaction completed
11:10
Reserved
R
0
9
set_dma_err
R
0
Set Non-Supported DMA command attempted or not enabled
8:6
Reserved
R
0
5
set_dma_mstr_parity_er
r
R
0
Set DMA master set or observed parity error (PERR)
4
set_dma_err_parity
R
0
Set DMA Detected parity error (PERR)
3
Reserved
R
0
2
set_dma_r_mabort
R
0
Set DMA Received Master Abort
1
set_dma_r_tabor
R
0
Set DMA Received Target Abort
0
Reserved
R
0
Offset 0x04 0FE0
PCI Interrupt Status
This register represents the status of direct access to Document title variable and PCI slave events.
31:27
Reserved
R
0
26
pcii_wr_err
R
0
Interrupt on PCI DTL initiator write error ag
25
pcii_rd_err
R
0
Interrupt on PCI DTL initiator read error ag
24
xio_wr_err
R
0
Interrupt on XIO DTL target write error ag
23
xio_rd_err
R
0
Interrupt on XIO DTL target read error ag
22
pcir_wr_err
R
0
Interrupt on mmio register DTL target write error ag
21
pcir_rd_err
R
0
Interrupt on mmio register DTL target read error
20
pwrstate_chg
R
0
Power management register has been changed
19
Reserved
R
0
18
pci2_wr_err
R
0
Interrupt on PCI2 DTL target write error ag
17
pci2_rd_err
R
0
Interrupt on PCI2 DTL target read error ag
16
pci1_wr_err
R
0
Interrupt on PCI1 DTL target write error ag
15
pci1_rd_err
R
0
Interrupt on PCI1 DTL target read error ag
14
pci_xio_ack_done
R
0
Rising edge of xio_ack has been observed
13:12
Reserved
R
0
11
serr_seen
R
0
SERR observed on PCI bus
10
Reserved
R
0
Table 8: Registers Description
Bit
Symbol
Acces
s
Value
Description