
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 6: Boot Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
6-4
2.2 Boot Module Operation
The following presents a high level block diagram of the boot module.
The four main components of the boot module are:
1. The MMIO to the DCS bus interface.
2. The I2C Master Interface & Control.
3. The Boot Control & State Machine.
2.2.1
MMIO Bus Interface
The MMIO bus sub-module contains only the master interface. Therefore despite the
general rule there is no MODULE_ID for the boot module and the master interface
module can only perform writes. It does not perform reads from other modules sitting
on the DCS bus. As a master, this module writes full 32-bit words to the DCS bus.
These write requests are then routed to the appropriate MMIO register or to the MMI.
2.2.2
I2C Master
Depending on the state of the BOOTMODE[1:0] pins, the I2C master interface gets
activated after the reset is released. If the BOOTMODE[1:0] is equal to 0x3 then the
boot module takes over the control of the I2C interface. The data received from the
external EEPROM is decoded by the boot state machine. The MMIO bus sub-module
is activated to write data on the DCS bus per the command encoding described in
Section 2.3. The I2C master does not arbitrate for the I2C bus since it is expected that there will be no other bus masters during the boot process. However, the I2C master
does allow clock stretching by the slave (here the EEPROM). The clock stretching is
not expected from the EEPROM but the feature is there in order to meet the I2C
Figure 1:
Boot Block Diagram
#2
Optional 2 to
64 Kilobytes
EEPROM
with custom
RESET Module
PNX15xx
Internal
Boot
Script
#1
Boot Module
MMIO to DCS
Bus Interface
peri_rst_n
27 MHz
(clk_27)
2
8
BOOT_MODE[7:0]
DCS Bus
I2C
I2C Control