
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 2: Overview
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
2-11
The TM3260 is responsible for all media processing and real-time processing
functions within the PNX15xx Series. It runs a small real-time operating system,
pSOS, which allows it to respond efciently and predictably to real-time events.
The TM3260 is capable of operating in little or big-endian mode. The mode is chosen
shortly after CPU startup by setting the endian bit in the Program Control Status
Word (PCSW).
Debug of software running on TM3260 is performed using an interactive source
debugger with a PC JTAG plug-in board. The PC talks to the TM3260 through the
PNX15xx Series JTAG pins. The TMDBG module provides an improved version of
the PNX1300 Series JTAG debug port. The PNX15xx Series is in standalone mode.
TM3260 media processor features are presented bellow.
Table 4: TM3260 Characteristics
TM3260 VLIW CPU Features
ISA
PNX1300 Series, with 32-bit RISC style load/store/compute instruction set and an extensive set of
8-, 16-bit SIMD multimedia instructions
Instructions
5 RISC or SIMD instructions every clock cycle
Data types
boolean, 8-, 16- and 32-bit signed and unsigned integer, 32-bit IEEE oats
Functional units
5 CONST, 5 Integer ALU’s, 5 multi-bit SHIFTERs, 3 DSPALU’s, 2 DSPMUL, 2 IFMUL, 2 FALU, 1
FCOMP, 1 FTOUGH (divide, sqrt) 3 BRANCH, 2 LD/ST
Caches
64 KB 8-way set associative ICache
16 KB 8-way set associative dual-ported Dcache
Cache policies
critical word rst rell, write-back, write-allocate, automatic heuristic hardware prefetch
Line size
64 bytes (both ICache and DCache)
MMU
none, virtual = physical, full 4 GB space supported
Protection
Base, limit style protection, where CPU can be set to only use part of system DRAM, and hardware
ensures no references take place outside this range
Multipliers
up to 2 32x32-bit integer multiplies per clock
up to 2 32-bit IEEE oating point multiplies per clock
up to 4 16x16-bit multiply-adds per clock
up to 8 8x8-bit multiplies per clock
Debug
JTAG based software debugger, including hardware breakpoints for instruction and data addresses
Register le
128 entry 32-bit register le
Interrupts
64 auto-vectoring interrupts, with 8 programmable priority levels
Timers
Four 32-bit timers/counters are provided. A wide selection of sources allows them to be used for
performance analysis, real-time interrupt generation and/or system event counting
System Interface
The TM3260 runs asynchronously with respect to system DRAM, and can operate at a frequency
lower than system DRAM to save power, or higher than system DRAM to gain performance
Software
Development
Environment
The TM3260 is supported by the advanced C/C++ compiler tools available for the PNX1300 Series
family
Application Software
Architecture
Applications use the TSSA, Trimedia Streaming Software Architecture, allowing modular
development of audio, video processing functions