
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 27: Power Management
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
27-2
The CPU writes/sets the device's POWERDOWN control bit (usually bit 31 of
offset 0xFF4). Setting this bit causes the device to power down elements such as
memories and register les.
Remark: This bit does NOT gate the internal module clock or other clocks as clock
gating is not allowed inside a module.
After setting the powerdown bit, none of the device's registers is accessible,
except the one containing the POWERDOWN bit, which is 100% operational.
– Reads from any other register do not hang.
– Writes to any register (except the POWERDOWN bit register) are completed
fully or result in an error.
The CPU programs the Clock module to stop/slow down the clock signals. This
assures the Clock module is stopped in a controlled way (no glitches/illegal
periods).
At this point, the register with the POWERDOWN bit is still the only accessible
register and the block is fully powered down.
1.1.3
Peripheral Module Wakeup Sequence
Waking up a module is also under CPU control and is the reverse sequence to
powerdown:
Program the Clock module so that all related clock sources are set to their normal
operational frequencies.
Reset the POWERDOWN bit in the module.
Set up the module's conguration registers if needed.
Enable the module.
1.1.4
TM3260 Powerdown Modes
The TM3260 CPU has two modes: Partial Powerdown and Full Powerdown.
Partial Powerdown Mode
The TM3260 CPU enters partial powerdown mode by performing a 'store' to a
specic MMIO address (the POWERDOWN register). The TM3260 then nishes any
pending transactions and go into a partial powerdown. In partial powerdown mode,
cycle counters, timers and interrupt logic in the TM3260 are still active. The TM3260
CPU wakes up from partial powerdown when an interrupt occurs or there is an
access to its MMIO space. This commonly used by the idle task in an operating
system.
Full Powerdown Mode
The TM3260 also have an externally-initiated full power shutdown mode i.e., no
wakeups when an interrupt occurs. Entering this mode is requested by asserting an
input signal to the TM3260. When this signal is asserted, the TM3260 nishes
pending transactions and gates-off its core clock.