
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 12: Video Input Processor
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
12-28
19
Unused
-
18
CSM_D1_TWOS
R/W
0
Offset coefcient D1 type
0 = unsigned
1 = signed
17:10
CSM_D1[7:0]
R/W
0
Offset coefcient D1
9
Unused
-
8
CSM_D0_TWOS
R/W
0
Offset coefcient D0 type
0 = unsigned
1 = signed
7:0
CSM_D0[7:0]
R/W
0
Offset coefcient D0
Offset 0x10 6230
Color space matrix offset coefcients E0 - E2
31:30
Unused
-
29:20
CSM_E2[9:0]
R/W
0
Offset coefcient E2, two’s complement
19:10
CSM_E1[9:0]
R/W
0
Offset coefcient E1, two’s complement
9:0
CSM_E0[9:0]
R/W
0
Offset coefcient E0, two’s complement
Color Keying Control Registers
Offset 0x10 6284
Color Key Components
31: 24 CKEY_ALPHA
R/W
0
Alpha value
Denes the alpha value to be used for keyed samples.
23: 0
reserved
Video Output Format Control Registers
Offset 0x10 6300
Video Output Format
31:30
PSU_BAMODE
R/W
0
Base address mode
00 = single set (e.g. progressive video source)
base 1-3 according to number of planes (plane 1-3)
01 = reserved
10 = alternate sets each eld (e.g. interlaced video source)
base 1-3, odd eld (plane 1-3)
base 4-6, even eld (plane 1-3)
11 = alternate sets each eld and frame (e.g. double buffer mode)
packed modes only, frame index is set to 1 if cfen=0, frame index is
incremented after capturing even eld before capturing odd, base
address byte offset is dened in PSU_OFFSET1
base 1, odd eld 1st frame (plane 1 only)
base 2, even eld 1st frame (plane 1 only)
base 3, odd eld 2nd frame (plane 1 only)
base 4, even eld 2nd frame (plane 1 only)
29:14
reserved
-
13
PSU_ENDIAN
R/W
0
Output format endianess
0: same as system endianess
1: opposite of system endianess
12
reserved
-
Table 10: Video Input Processor (VIP) 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description