
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 5: The Clock Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
5-50
9:8
Aligner_adjust_area2
R/W1
10
Adjust the aligner for the clock going to area 2
7:6
Aligner_adjust_area1
R/W1
10
Adjust the aligner for the clock going to area 1
5:4
Aligner_adjust_l_area0
R/W1
10
Adjust the aligner for the late clock going to area 0
3:2
Aligner_adjust_e_area0
R/W1
10
Adjust the aligner for the early clock going to area 0
1:0
Aligner_adjust
R/W1
10
Adjust the aligner for the 3ns aligner
The below values apply to each of the above except the 25:24 bits
11 : adds to the clock latency
01, 10 : medium clock latency (default)
00 : decreases the clock latency
Offset 0x04,7514-FDC
RESERVED
Interrupt Registers
Offset 0x04,7FE0
INTERRUPT STATUS
31
VDO_CLK2_present
R
0
1: Clock present
0: Clock NOT present
30
VDI_CLK2_present
R
0
1: Clock present
0: Clock NOT present
29
ao_sckin_present
R
0
1: Clock present
0: Clock NOT present
28
ai_sckin_present
R
0
1: Clock present
0: Clock NOT present
27
VDI_CLK1_present
R
0
1: Clock present
0: Clock NOT present
26:5
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
4
VDO_CLK2 (clk_fgpo)
R
0
1: Clock interrupt
3
VDI_CLK2 (clk_fgpi)
R
0
1: Clock interrupt
2
AO_SCK
R
0
1: Clock interrupt
1
AI_SCK
R
0
1: Clock interrupt
0
VDI_CLK1 (clk_vip)
R
0
1: Clock interrupt
Offset 0x04,7FE4
INTERRUPT ENABLE
31:5
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
4
VDO_CLK2 (clk_fgpo)
R/W
0
1: Interrupt enabled
0: Interrupt NOT enabled
3
VDI_CLK2 (clk_fgpi)
R/W
0
1: Interrupt enabled
0: Interrupt NOT enabled
2
AO_SCK
R/W
0
1: Interrupt enabled
0: Interrupt NOT enabled
1
AI_SCK
R/W
0
1: Interrupt enabled
0: Interrupt NOT enabled
Table 11: CLOCK MODULE REGISTERS …Continued
Bit
Symbol
Acces
s
Value
Description