
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 28: Pixel Formats
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
28-2
2.
Summary of Native Pixel Formats
subsystems that support them.
The layout shown in
Figure 1 is the way that a unit ends up in a CPU register given a
unit size (8, 16 or 32-bit) load operation, regardless of the PNX15xx Series endian
mode of operation.
Table 1: Native Pixel Format Summary
Name
Note
VIP
Out
MPG
Out
MBS
In
MBS
Out
2D Draw
Eng (2)
QVCP
In
1 bpp indexed
CLUT entry = 24-bit color + 8-bit alpha
x
2 bpp indexed
xx
4 bpp indexed
xx
8 bpp indexed
xx
x
RGBa 4444
16-bit unit, containing 1 pixel with alpha
(1)
x
RGBa 4534
(1)
x
RGB 565
16-bit unit, containing 1 pixel, no alpha
(1)
x
RGBa 8888
32-bit unit, containing 1 pixel with alpha
(1)
x
packed YUVa 4:4:4
32-bit unit containing 1 pixel with alpha
x
packed YUV 4:2:2 (UYVY)
16-bit unit, 2 successive units contain 2
horizontally adjacent pixels, no alpha
xx
x
packed YUV 4:2:2 (YUY2, 2vuy)
x
planar YUV 4:2:2
3 arrays, 1 for each component
x
semi-planar YUV 4:2:2
2 arrays, 1 with all Ys, 1 with U and Vs
x
planar YUV 4:2:0
3 arrays, 1 for each component
x
semi-planar YUV 4:2:0
2 arrays, 1 with all Ys, 1 with U and Vs
x
semi-planar 10-bit YUV 4:2:2
2 arrays, 1 with all Ys, 1 with U and Vs
3Ys are packed in 4 Bytes and 3 sets of
UV pixels are packed in 8 Bytes
x
semi-planar 10-bit YUV 4:2:0
2 arrays, 1 with all Ys, 1 with U and Vs
3Ys are packed in 4 Bytes and 3 sets of
UV pixels are packed in 8 Bytes
x
Packed 10-bit YUV 4:2:2(UYVY)
6Ys and 3UVs are packed in 16 Bytes.
x
(1) The VIP is capable of producing RGB formats, but not when performing horizontal scaling.
(2) Shown are the 2D Drawing Engine frame buffer formats where drawing, rasterops and alpha-blending of surfaces can be
accelerated. The 2D Drawing Engine host port also supports 1 bpp monochrome font/pattern data, and 4 and 8-bit alpha
only data for host initiated anti-aliased drawings.