
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 5: The Clock Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
5-35
Offset 0x04,7008
PLL2_CTL
Reset values set for expected frequencies for faster boot-up, shorter boot code.
31:30
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
29
Turn Off Acknowledge
R
-
Indicates that during a frequency change that the clock has been
driven low.
28
PLL Lock
R
-
A one indicates that the PLL is locked
27:24
pll2_adj
R/W
0
23:21
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
20:12
pll2_n
R/W
0x2E
11:10
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
9:4
pll2_m
R/W
0x5
3:2
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
1
pll2_pd
R/W
0
1: powerdown PLL2
0
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Offset 0x04,700C
PLL1_7GHZ_CTL
31:3
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
2
pll1_7ghz_pd
R/W
0
1: powerdown PLL1_7GHZ
1:0
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
DDS Registers
Offset 0x04,7010
DDS0_CTL
31
Enable
R/W
0
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
30:0
dds0_ctl[30
:0]
R/W
0x07684
bd0
31-bit DDS0 control (default = 50 MHz)
Offset 0x04,7014
DDS1_CTL
31
Enable
R/W
0
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
30:0
dds1_ctl[30:0]
R/W
0x04000
000
31-bit DDS1 control (default = 27 MHz)
Offset 0x04,7018
DDS2_CTL
31
Enable
R/W
0
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
30:0
dds2_ctl[30:0]
R/W
0x04000
000
31-bit DDS2 control (default = 27 MHz)
Table 11: CLOCK MODULE REGISTERS …Continued
Bit
Symbol
Acces
s
Value
Description