
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 11: QVCP
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
11-58
2
Alpha_use
R/W
0
Controls which alpha value is used for blending in the layer mixer
stage
1 = Use previous alpha
0 = Use alpha of current layer
1
422:444_Interspersed
R/W
0
Chroma upsample lter operation mode
1 = use this mode if input samples are arranged interspersed
0 = use this mode if input samples are arranged co-sited
0
422:444_Enable
R/W
0
Chroma upsample lter enable
1 = chroma upsample lter is enabled
0 = chroma upsample lter is in bypass mode
Offset 0x10 E240
Layer Status/Control
31:10
Unused
-
9
Layer upload
R
-
This bit indicates if the register upload into the shadow area is still in
progress.
1 = New register upload possible, previous upload is complete
0 = Upload in progress, DO NOT reprogram any registers as the
results are undetermined
8:1
Unused
-
0
LayerN_Enable
R/W
0
0 = Disable layer N
1 = Enable layer N
This register reads always 0 if the screen timing generator is not
enabled
Offset 0x10 E244
LUT Programming
31:24
Alpha
R/W
0
Alpha value for LUT programming
23:16
Red
R/W
0
Red value for LUT programming
15:8
Green
R/W
0
Green value for LUT programming
7:0
Blue
R/W
0
Blue value for LUT programming
Offset 0x10 E248
LUT Addressing
31:24
LUTAddress
R/W
0
Address register for LUT programming, no auto-increment is
supported.
23:9
Unused
-
8
Host_Enable
R/W
0
This enables read/write access by the host:
1 = Host access enabled.
0 = Host access disabled.
7:2
Unused
-
1
Lut_enable
R/W
0
LUT enable signal
0 = bypass LUT
1 = Allow data to ow through LUT
0
Unused
-
Offset 0x10 E24C
Pixel Key AND Register
31:24
PixelKeyAND
R/W
0xFF
The bits 31:24 in 32 bpp mode are ANDed with this mask (input for
KEY2).
Not available when PF_10B_MODE(see 0x10 E2BC)is on.
Table 20: QVCP 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description