
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 14: FGPI: Fast General Purpose Interface
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
14-7
Remark: SOFTWARE_RESET does not reset MMIO bus interface registers. Any
DMA transfers will be aborted during a SOFTWARE_RESET. All registers are reset to
the Reset Value shown in the Register Description section.
2.2 Base Addresses
Two base address registers are used to point to main memory buffers in a double
buffering scheme. Addresses are forced into 32-bit address alignment.
2.3 Sample (data) Size
Data size (width) per sample is set to either 8, 16, or 32 bits using
FGPI_CTL.SAMPLE_SIZE bit eld. For 8-bit samples, four samples are packed into
one 32-bit word. For 16-bit samples, two samples are packed 2 into one 32-bit word.
Byte order, with which the data is written to memory, is controlled by the global
PNX15xx Series endian mode. The endian state only affects 16 and 32-bit sample
sizes.
Figure 3 shows how data is stored in memory if data input to the FGPI does not
match the setting of the FGPI_CTL.SAMPLE_SIZE bit eld. Settings for the PNX15xx
Series Input Router will affect the “unknown data” received.
2.4 Record or Message Size
In record mode:
The number of samples per record is set by FGPI_REC_SIZE eld. This is the
amount of samples that will be captured after each record start event.
In message mode:
Maximum number of samples per message is set by FGPI_REC_SIZE eld. The
end of a message is signaled by the active fgpi_stop edge. If the message length
is greater than the programmed value in the FGPI_REC_SIZE register, the
message is truncated and a OVERFLOW interrupt is generated.
Figure 3:
Input data width not equal to sample size setting
FGPI_CTL.SAMPLE_SIZE = 32-bit
8-bit data input to FGPI
12
3
4
memory address
a
a+4
a+8
a+12
bit 0
bit 31
12
16-bit data input
a
a+4
FGPI_CTL.SAMPLE_SIZE = 16-bit
8-bit data input to FGPI
1
2
a
3
4
a+4
unknown
data