
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 12: Video Input Processor
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
12-21
3.2 Register Table
Table 10: Video Input Processor (VIP) 1 Registers
Bit
Symbol
Acces
s
Value
Description
Operating Mode Control Registers
Offset 0x10 6000
VIP Mode Control
31:30
VID_CFEN[1:0]
R/W
0
Video window capture eld enable
00 = capture disabled
01 = capture odd only
10 = capture even only
11 = capture both
29
VID_OSM
R/W
0
Video capture one shot mode
0 = continuously capture elds selected by CFEN
1 = capture elds selected by CFEN only once
28
VID_FSEQ
R/W
0
video capture eld sequence
0 = capture elds starting with any eld
1 = capture elds starting with odd eld
setting has no effect unless VID_CFEN is set to capture both
27:26
AUX_CFEN[1:0]
R/W
0
Auxiliary window capture enable
00 = capture disabled
01 = capture odd only
10 = capture even only
11 = capture both
25
AUX_OSM
R/W
0
Auxiliary capture one shot mode
0 = when auxiliary wrap event is reached, buffer wraps around
1 = when auxiliary wrap event is reached, capturing stops
24
AUX_FSEQ
R/W
0
Auxiliary capture eld sequence
0 = capture elds starting with any eld
1 = capture elds starting with odd eld
setting has no effect unless AUX_CFEN is set to capture both
23:22
AUX_ANC[1:0]
R/W
0
ANC data capture enable
00 = no ANC data captured
01 = odd ANC eld blocks. (masked DATA_ID_0 bit matched)
10 = even ANC eld blocks. (masked DATA_ID_1 bit matched)
11 = odd/even ANC eld blocks. (masked DATA_ID_* bit matched)
21
AUX_RAW
R/W
0
Auxiliary raw capture enable
0 = raw capture disabled
1 = raw capture enabled, all samples will be captured
when enabled, AUX_ANC and AUX_CFEN settings are ignored
20:18
reserved
17
RST_ON_ERR
R/W
0
Reset on error
Writing a one into this bit will automatically reset the block in case of
a pipeline error (e.g. illegal scaling ratio / FIFO overow)
16
SOFT_RESET
W
0
Soft reset
Writing a one into this bit will reset the block
15
reserved