
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 2: Overview
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
2-6
3.
System Resources
3.1 System Reset
The PNX15xx Series includes a system reset module. This reset module provides a
synchronous reset to internal PNX15xx Series logic and a reset output pin for
initialization of external system components. A system reset can be initiated in
response to a board level reset input pin, a software conguration write or as a result
of a programmable watchdog timer time-out. This watchdog timer is a fail-safe
recovery mechanism which may be enabled by software. When enabled, a periodic
interrupt is sent to the TM3260 CPU. If the CPU does not respond to the interrupt
within a programmable time-out period, then the system is assumed to be hung and
the system reset is asserted.
Boot also resets board level peripherals by asserting the SYS_RST_OUT_N pin.
3.2 System Booting
The PNX15xx Series boot method is controlled by the BOOT_MODE[7:0] pins’
resistive straps. The
Table 2 shows the main boot modes available. More details can
the code on these pins is sampled. The pins operate as GPIO pins after boot.
The PNX15xx Series on-chip TM3260 CPU is capable of direct standard Flash
execution to allow for booting. Note: Direct execution from NAND Flash, a.k.a. disk
Flash is not supported. Direct execution from ash, however, has very limited
performance. Hence, the TM3260 typically copies a Flash le to high-performance
system DRAM, and executes it in DRAM. That Flash le contains the self-
decompressing initial system software application. This multi-stage boot process that
starts a compressed code module minimizes system memory cost.
Table 2: PNX15xx Series Boot Options
BOOT_MODE
Description
000
Set up system, and start the TM3260 CPU from a 8-bit NOR Flash or ROM attached to PCI/
XIO
100
Set up system, and start the TM3260 CPU from a 16-bit NOR Flash or ROM attached to PCI/
XIO
001
Set up system, and start the TM3260 CPU from a 8-bit NAND Flash attached to PCI/XIO
101
Set up system, and start the TM3260 CPU from a 16-bit NAND Flash attached to PCI/XIO
x10
Boots in host assisted mode with a default SubSystem ID of 0x1234 and a default System
Vendor ID of 0x5678. This boot mode can be used for standalone system but should not be
used for a PC PCI plug-in card since such a board requires a personal System Vendor and
SubSystem ID. Instead the I2C boot EEPROM should be used.
s11
Boots from a I2C EEPROM attached to the I2C bus. EEPROMs of 2 KB - 64 KB size are
supported. The entire system can be initialized in a custom fashion by the boot command
structure. The I2C EEPROM holds write commands and writes data to internal MMIO registers
and to the main memory. BOOT_MODE[2] denes the speed of the I2C bus, i.e. 100 or 400
kHz.
other
Reserved