
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 24: TM3260 Debug
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
24-8
Remark: All references to instruction and data registers refer to JTAG instructions
and data registers only (not TM3260 instruction or data registers).
Data Registers
There are two 32-bit data registers, TM_DBG_DATA_IN and TM_DBG_DATA_OUT in
the MMIO space. Both can be connected in between TDI and TDO like the standard
Bypass and Boundary-Scan registers of JTAG.
The TM_DBG_DATA_IN register can be read or written to via the JTAG port.
The TM_DBG_DATA_OUT register is read-only via the JTAG port, so that
scanning out TM_DBG_DATA_OUT is non-destructive.
The TM_DBG_DATA_IN and TM_DBG_DATA_OUT are readable/writable from
the TM3260 processor via the usual load/store operations.
Control Registers
There are two control registers, TM_DBG_CTRL1 and TM_DBG_CTRL2, in MMIO
space.
The TM_DBG_CTRL registers are used for handshake between a debug monitor
running on a TM3260 CPU and a debugger front-end running on a host.
TM_DBG_CTRL1.ofull = 1 means that TM_DBG_DATA_OUT has valid data to be
scanned out. On the power-on reset of the PNX15xx Series,
TM_DBG_CTRL1.ofull = 0. TM_DBG_CTRL1.ofull is both readable and writable
via the JTAG tap. Writing 0 to TM_DBG_CTRL1.ofull via JTAG is a “remember”
operation i.e., TM_DBG_CTRL1.ofull retains its previous state. Writing 1 to
TM_DBG_CTRL1.ofull via JTAG is a ‘clear’ operation i.e., TM_DBG_CTRL1.ofull
becomes 0.
TM_DBG_CTRL2.ifull = 0 means that the TM_DBG_DATA_IN register is empty.
TM_DBG_CTRL2.ifull = 1 means that TM_DBG_DATA_IN has valid data and the
debug monitor has not yet copied it to its private area. Upon power on reset of the
TM3260 processor, TM_DBG_CTRL2.ifull = 0. TM_DBG_CTRL2.ifull is readable
Figure 3:
Additional JTAG Data and Control Registers
To TDO
TM_DBG_DATA_IN
TM_DBG_DATA_OUT
TM_DBG_CTRL1
From TDI
0
ifull
ofull
Unused Bits
0
31
0
1
Sleepless
Bit
2
Unused Bits
TM_DBG_CTRL2
1