
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 26: Memory Arbiter
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
26-2
After reset, the Arbiter is in “boot” mode and guarantees that each requesting agent is
given a “grant” to main memory (Round Robin is the default arbitration method).
2.1 Arbiter Features
Time-Division Multiple Access (TDMA) arbitration
– guarantees maximum allowed latency
– 128 TDMA slots
Priority arbitration
– guarantees minimum required bandwidth
– 16 Priority slots
Two level Round Robin arbitration
– provides equal opportunities to the lower priority “best effort” or DMA write
agents
– 16 round robin slots in the rst level
– 8 round robin slots in the second level
Dynamic arbitration scheme
– Two sets of arbitration parameters can be dened. Selection can be made
dynamically via software based on system needs.
2.2 ID Mapping
The
Table 1 shows the mapping of each module to an unique identication numbers.
The rst column shows the IDs when programing the TDMA wheel. The second
column indicates which ID number to use when programing the priority and
roundrobin list.
Table 1 also shows the amount of sub-arbitration for the given
modules. If not otherwise noted the amount of buffering per DMA channel is 256
bytes.
Table 1: Peripheral ID and Sub-Arbitration
TDMA
ID
Modules
DMA
Channels
Buffer size
Transaction
size
0x8
0x0
2DDE
1 x R, 1 x W
2 x 256-byte buffer
128 Bytes
0x9
0x1
PCI
2 x R, 2 x W
4 x 256-byte buffer
128 Bytes
0xA
0x2
QVCP
4 x R
4 x 512-byte buffer
128 Bytes
0xB
0x3
VIP
3 x W
3 x 256-byte buffer
128 Bytes
0xC
0x4
VLD
1 x R, 2 x W
3 x 256-byte buffer
128 Bytes
0xD
0x5
FGPI
2 x W
2 x 512-byte buffer
128 Bytes
0xE
0x6
Reserved
0xF
0x7
MBS (r)
3 x R
3 x 256-byte buffer
128 Bytes
0x0
0x8
MBS (w)
3 x W
3 x 256-byte buffer
128 Bytes
0x1
0x9
10/100 MAC
2 R x 3 W
10 x 32-byte buffer
32 Bytes
0x2
0xA
FGPO
2 x R
4 x 256-byte buffer
1 x 16-byte buffer
128 Bytes