
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 3: System On Chip Resources
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
3-21
VDI-to-FGPI mapping (continued)
up to 24-bit data capture
XX010:
VDI_V2
-> (clk_fgpi FF) -> fgpi_d_valid
VDI_D[23:0] -> (clk_fgpi FF) -> fgpi_data[23:0]
VDI_D[32]
-> (clk_fgpi FF) -> fgpi_start (*)
VDI_D[33]
-> (clk_fgpi FF) -> fgpi_stop (*)
00010:
“0”
-> fgpi_data[31:24]
01010:
“1”
-> fgpi_data[31:24]
10010:
VDI_D[23] -> (clk_fgpi FF) -> fgpi_data[31:24]
11010:
“0”
-> fgpi_data[31:24]
(*) For VDI_MODE[7] = 0. When VDI_MODE[7] = 1, fgpi_start and
fgpi_stop are controlled by a simple pattern matching state
machine.
VDI-to-FGPI mapping (continued)
up to 32-bit data capture
XX011:
VDI_V2
-> (clk_fgpi FF) -> fgpi_d_valid
VDI_D[31:0] -> (clk_fgpi FF) -> fgpi_data[31:0]
VDI_D[32]
-> (clk_fgpi FF) -> fgpi_start (*)
VDI_D[33]
-> (clk_fgpi FF) -> fgpi_stop (*)
(*) For VDI_MODE[7] = 0. When VDI_MODE[7] = 1, fgpi_start and
fgpi_stop are controlled by a simple pattern matching state
machine.
Offset 0x06 3004
VDO_MODE
31:8
Unused
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
7
VDO_MODE
R/W
0
If set to ‘1’ and VDO_MODE[2:0] set to 0, then in addition to the
QVCP to the TFT interface mapping the FGPO 8-bit LSBs map as
follows:
VDO_D34
-> (clk_fgpo FF) -> fgpo_data[7]
FGPO_BUF_SYNC -> (clk_fgpo FF) -> fgpo_data[6]
FGPO_REC_SYNC -> (clk_fgpo FF) -> fgpo_data[5]
VDO_D33
-> (clk_fgpo FF) -> fgpo_data[4]
VDO_D32
-> (clk_fgpo FF) -> fgpo_data[3]
VDO_D[2:0]
-> (clk_fgpo FF) -> fgpo_data[2:0]
This mode allows to have, for example, a ITU-656 video stream
coming out of FGPO while the QVCP drives a 24-bit TFT LCD
panel.
Table 8: Global Registers …Continued
Bit
Symbol
Acces
s
Value
Description