
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
7-32
7:5
max_burst_size
R/W
0
PCI transaction will be split into multiple transactions. Max size:
000 = 8 data phase
001 = 16 data phase
010 = 32 data phase
011 = 64 data phase
100 = 128 data phase
101 = 256 data phase
110 = 512 data phase
111 = No restriction in transfer length
4
init_dma
R/W
0
Initiate DMA transaction. This bit is cleared by the DMA engine
when it begins its operation.
3:0
cmd_type
R/W
0
Command to be used for DMA. This eld is restricted to memory
type or IO type commands as dened in the PCI 2.2 spec.
Offset 0x04 0810
XIO Control Register
31:2
Reserved
R
0
1
xio_ack
R
Live XIO_ACK status bit.
0
Reserved
R
0
Offset 0x04 0814
XIO Sel0 Prole
This register sets up the prole of the XIO select 0 line. All times are in reference to PCI clocks.
31:25
Reserved
R
0
24
misc_ctrl
R/W
0
68360: 1 synchronous DSACK; 0 asynchronous DSACK.
NOR: Not used
NAND: Not used
IDE: Not used
23
en_16bit_xio
R/W
0
0 = 8 bit XIO device
1 = 16 bit XIO device
22
sel0_use_ack
R/W
0
0 = Fixed wait state
1 = Wait for ACK
Not used for IDE.
21:18
sel0_we_hi
R/W
0
68360: DS time high.
NOR: WN time high
NAND: REN prole, [19:18] low time; [21:20] high time
IDE: DIOR and DIOW high time
17:14
sel0_we_lo
R/W
0
68360: Not used.
NOR: WN time low
NAND: WEN prole, [15:14] low time; [17:16] high time
IDE: DIOR and DIOW low time
13:9
sel0_wait
R/W
0
68360: DS time low if using xed timing.
NOR: OEN time low if not using ACK.
NAND: Delay between address and data phase if not using ACK,
delay until monitoring ACK.
IDE: Not used.
8:5
sel0_offset
R/W
0
Starting address offset from start address of XIO aperture, in 8M
increments. This eld must be naturally aligned with the size of the
prole.
Table 8: Registers Description
Bit
Symbol
Acces
s
Value
Description