參數(shù)資料
型號: 84C300A
廠商: LSI Corporation
英文描述: 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器)
中文描述: 4端口快速以太網(wǎng)控制器(四端口快速以太網(wǎng)控制器)
文件頁數(shù): 52/56頁
文件大?。?/td> 523K
代理商: 84C300A
84C300A 4-Port
Fast Ethernet Controller
4-52
MD400152/E
Revision History
Page 30 - In Sections: CRC Error Counter, Runt Frame Counter, Alignment Error Counter, Transmit Collision Counter
Receive Collision Counter; copy has changed ... To read this counter, two consecutive reads need to be
performed to the same address location. The first read, reads out the high byte followed by the second, that will
read out the low byte. Upon reading ...
Page 31, DC Characteristics:
- Clock Input High Voltage (Limits Min.), has been changed from 3.5 to 4.0.
Page 32, AC Characteristics:
- TDBD (min) has been changed from 100 to 0.5 RXC/TXC Cycles + 10 ns.
- TDBD (max) has been changed from 200 to 1.5 RXC/TXC Cycles + 50 ns.
- TDBD, All Other Registers (min) is now 10.
- TDBR (min) has been changed from 7 to 1.5.
- TDBR (max) has been changed from 20 to 5.5.
- TDBS (min) has been changed from 10 to 6.
- TDBS (max) has been changed from 20 to 32.
- Symbol THARhas been changed to THA.
- THA Parameter has been changed from A
0-2
/Reg PS[1:0] Hold to A[3:0] Hold.
- Symbol TSARhas been changed to TSA.
- TSA Parameter has been changed from A
0-2
/Setup to A[3:0] Setup.
- THCS row is new.
- Symbol TWCHhas been changed to TRWH
- TRWH Parameter has been changed from RD/WR High Width, to RD High Width.
- TRWH (min) has been changed from 200 to 1 TXC/RXC Cycle.
- Symbol TWCLhas been changed to TRWL
- TRWL Parameter has been changed from RD/WR Low Width to RD Low Width.
- TRWL (min) has been changed from 200 to 1.5 TXC/RXC Cycles + 70 ns.
- TWWH row is new.
- TWWL row is new.
Pages 33 to 40, has been deleted and replaced with new Tables and Timing Diagrams, also the pagination has changed.
- Page 33, New Timing Diagrams, 5.01 Command/Status Interface Read Timing, and 5.02 Command/Status
Interface Write Timing.
- Page 34, New Timing Diagrams, 6.01 Ethernet Transmit Interface Timing, and 6.02 Ethernet Receive Interface
Timing.
- Page 34, New Table 6.0 Ethernet Transmit and Receive Interface Timing.
- Page 35, New Table, 7.0 Transmit Data Interface Timing.
- Page 36, New Timing Diagram, 7.01 Transmit Data Interface Write Timing 1.
- Page 37, New Timing Diagram, 7.02 Transmit Data Interface Write Timing 2.
- Page 38, New Table, 8.0 Receive Data Interface Timing.
- Page 39, New Timing Diagram, 8.01 Receive Data Interface Read Timing 1.
- Page 40, New Timing Diagram, 8.02 Receive Data Interface Read Timing 2.
- Page 41, New Table, 9.0 Transmit Data Interface Timing on Exception Conditions.
- Page 42, New Timing Diagram, 9.0 Transmit Data Timing on Exception Conditions.
- Page 43, New Table, 10.0 Receive Data Interface Timing on Exception Conditions.
- Page 44, New Timing Diagram, 10.0 Receive Data Timing on Exception Conditions.
12/4/96
Page 18; Internal Port Register Addressing Table
- Register Description Read, Dribble Error Counter has been changed to Alignment Error Counter.
Page 47; 208 Pin PQFP Dimension Diagram, illustration has changed.
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