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參數資料
| 型號： | 84C300A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller(四端口快速以太網控制器) |
| 中文描述： | 4端口快速以太網控制器（四端口快速以太網控制器） |
| 文件頁數： | 27/56頁 |
| 文件大小： | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-27
MD400152/E
3.6.5 Receive Command Register
A port’s Receive Command Register has two primary
functions, it specifies the Address Match Mode, and it
specifies which types of receive frames will be received
and if an associated interrupt will be produced. To set
interrupt conditions the Receive Command Register uses
bits 5 through 0 in conjunction with bit #7 of configuration
register #1.
Bit 7 of configuration register #1 is a general receive
interrupt disable. Setting this bit HIGH disables all receive
interrupt conditions even f one of the bits 0 through 5 n the
receive command register is set HIGH. This allows ena-
bling reception of receive packets with errors without an
interrupt being produced. With the general receive inter-
rupt bit LOW, a receive interrupt can be produced on one
or more of he ollowing conditions by setting ts associated
interrupt enable bit in the receive command register:
Receive Command Register Format
7
6
5
4
3
2
1
0
Receive
Command
Register
Receive
Command
Register
Values
Definition
R/W
Default
Values
Upon Reset
Bit 0
1
Enables Reception of packets with a receive overflow error
without generating an RXDC. If Bit 7 of Configuration
Register #1 is ‘0’, receive overflow error will assert interrupt
if this bit is ‘1’.
Automatically discards packets with a receive overflow error
by generating an RXDC.
Enables Reception of packets with a receive CRC error
without generating an RXDC. If Bit 7 of Configuration
Register #1 is ‘0’, receive CRC error will assert interrupt
if this bit is ‘1’.
Automatically discards packets with a receive CRC error by
generating an RXDC.
Enables Reception of oversized packets without generating
an RXDC. If Bit 7 of Configuration Register #1 is ‘0’,
oversized receive packet will assert interrupt if this bit is ‘1’.
Automatically discards oversized receive packets by
generating an RXDC.
Enables Reception of undersized packets without generating
an RXDC. If Bit 7 of Configuration Register #1 is ‘0’,
undersized receive packet will assert interrupt if this bit is ‘1’.
Automatically discards undersized receive packets by
generating an RXDC.
If Bit 7 of Configuration Register #1 is ‘0’, setting this bit to ‘1’
asserts interrupt as an indication of the first 12 bytes received.
If Bit 7 of Configuration Register #1 is ‘0’, setting this bit to ‘1’
asserts interrupt as an indication of the reception of a good
packet for debugging purposes.
Match mode 0.
Please refer to the following table for match mode definitions.
Match mode 1.
Please refer to the following table for match mode definitions.
W
0
0
W
0
Bit 1
1
W
0
0
W
0
Bit 2
1
W
0
0
W
0
Bit 3
1
W
0
0
W
0
Bit 4
1
W
0
Bit 5
1
W
0
Bit 6
Bit 7
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