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參數(shù)資料
| 型號： | 84C300A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（四端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 29/56頁 |
| 文件大?。?/td> | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-29
MD400152/E
Receive packet status is also included as part of the final
double word of receive data for a packet that is not
discarded. The final double word of a packet as read from
the receive FIFO contains the status and the byte count for
that packet with the status appearing as the least signifi-
cant word of the double word and the byte count appearing
in the two most significant bytes of the double word. The
status read through the FIFO has the same bit values as
the receive status register except for the following:
Bit 7: RXABORT During Reception
Bit 8: Read Error Condition
Bit 7 is an indication that the RXABORT pin was pulsed
HIGH while CSN was HIGH for the packet. Bit 8 Indicates
that some type of error has occurred in the receive FIFO
control circuitry with a result that the number of double
words written to the FIFO as indicated by the byte count
portion of the status double word does not equal the
number of double words read rom he FIFO or he packet.
The Status Double Word Format
31
Note:
This status double word gets appended to the packet in
the same format for both Little and Big Endian modes.
16
8
0
Reserved
Byte Count
Status Register Word
This ype of error can only be caused by some ype of noise
glitch or other unusual occurrence within the receive
section. Any packet read from the FIFO with Bit 8 of the
status set HIGH should be considered to have bad data.
This condition should never occur in a properly designed
application. If status s ever read with Bit 8 being HIGH, he
receive section will automatically reset itself to provide a
clean starting point for further packet reception.
Clearing Interrupts
Both receive and transmit interrupts for a port are
combined into a single interrupt signal which then
goes to that port's INT output pin. The interrupt signal
within a port in the chip is actually the result of the
receive/transmit status register outputs and the re-
ceive/transmit command register nterrupt enable bits
that are set. To clear an interrupt the status that
caused the interrupt needs to be cleared. This can be
accomplished by reading the transmit status register
and/or the receive status register.
3.6.7 Configuration Registers
Configuration Register #1
Allows for control of a port’s various transmit and receive
features. Set to all 0’s after reset.
Mode A: Group Address Mode
In this mode the last 4 bits of the serial receive data
stream for the destination address are masked out in
address comparison. This means that when the
destination address is compared against the value
Bit
0
Value
‘1’
‘0’
‘1’
Definition
Enables Group Address Mode.
Disables Group Address Mode.
Detection of a 2.5 MHz TXCLK
from the Transceiver.
Detection of a 25 MHz TXCLK from
the Transceiver
Enables Transmit packet
Autopad Mode.
Enables transmit no preamble
mode.
Refer to TABLE A
Enables transmit no CRC mode.
Refer to TABLE A
Enables Receive CRC Mode.
Disables Receive Interrupts
R/W
W only
Default
0
Mode
A
R only
0
‘0’
1
‘1’
R/W
0
B
2
‘1’
R/W
0
C
3
4
5
6
7
‘1’
‘1’
‘1’
‘1’
‘1’
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
E
G
H
7
6
5
4
3
2
1
0
Configuration Register #1
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