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參數(shù)資料
| 型號： | 84C300A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（四端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 21/56頁 |
| 文件大小： | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-21
MD400152/E
pulsing the CLRRXERR input high for a minimum of
one RXRD_TXWR clock cycle. The RXINTEN input
must not change state for the duration of the time that
the CLRRXERR input is high.
Clearing Interrupts
Within one port, both receive and transmit interrupts
are combined nto a single nterrupt signal which then
goes to the INT output pin. The interrupt signal in the
chip s actually he result of he receive/transmit status
register outputs and the receive/transmit command
register interrupt enable bits that are set. To clear an
interrupt, the status that caused the nterrupt needs to
be cleared. This can be accomplished by reading the
transmit status register and/or the receive status
register.
3.4 SYSTEM INTERFACE
The chip system nterface consists of one receive/transmit
32-bit bidirectional data bus, one 8-bit bidirectional com-
mand/status data bus, and each busses respective control
signals. Receive FIFO data is read and Transmit FIFO
data is written over the RXTXDATA[31:0] bus, and Com-
mand/Status data is written or read over the bidirectional
CDST[7:0] data bus.
3.5 FIFO INTERFACE
3.5.1 Little Endian and Big Endian Format
The FIFO nterface control ncludes the BUSMODE bit 7 n
configuration register #2, which sets the 84C300A FIFO
interface to Big Endian or Little Endian byte transmit/
receive data order. In Big Endian mode, data written to the
transmit FIFO is transmitted most significant byte of the
RXTXDATA bus first and least significant byte of the
RXTXDATA bus last. In Little Endian mode, the least
significant byte of each double word s transmitted first and
the most significant byte of each double word is transmit-
ted ast. On the receive side, f Big Endian mode s n effect
then the first data bytes received are assumed to be the
most significant bytes of the double word and appear on
the most significant portion of the RXTXDATA bus for
receive FIFO reads. The receiver reverses this order f the
chip is in Little Endian mode. The value of the BUSMODE
bit has no effect on the operation of the 84301 register
interface. It is important to note that the operation of the
byte enables remain the same for both modes.
3.5.2 Transmit FIFO Interface
To determine f the transmit FIFO for any of the chips ports
has reached its threshold number of double words of
space available, all our TXRDY outputs can be enabled by
driving the TXINTEN input low. The TXRDY output for a
port will be high if there is enough space available in the
port's transmit FIFO to meet or exceed the programmed
threshold value.
Once one of the TXRDY outputs is determined to be high,
that port’s Transmit FIFO can be written. To write to a
port’s Transmit FIFO, the TXWREN and TXINTEN inputs
must be asserted ow and at east one of the RXTXBE byte
enables must be ow for each write cycle. The value of the
RXTXPS nputs determines which port s being written. All
of the above inputs are clocked into the chip on the high
going edge of the RXRD_TXWR clock input which also
acts as the FIFO write strobe. Because of this pipe lining
the actual FIFO write will occur one RXRD_TXWR cycle
after the assertion of the Transmit FIFO interface control
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