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參數(shù)資料
| 型號： | 84C300A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（四端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 18/56頁 |
| 文件大?。?/td> | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-18
MD400152/E
output will go low and stay low until the TXRET flag is
cleared. Similar to a port's receive discard signal, a
transmit retry signal going to the external TXRET pin is
latched upon a transmit retry condition and held high until
cleared. Until a port's transmit retry signal is cleared, no
new transmit packets can be written to the transmit FIFO.
3.2.6 Detecting and Clearing a Transmit Retry
Condition
To enable the output drivers for the four TXRET pins, the
the TXINTEN nput s driven ow. Once a Tx retry condition
is detected, that port's internal Tx retry signal can be
cleared by first setting the RXTXPS[1:0] inputs to point to
that port. Then by driving the TXINTEN input low and then
pulsing the CLRTXERR input high for a minimum of one
RXRD_TXWR clock cycle, this will clear that port's TXRET
signal. The RXTXPS [1:0] and TXINTEN inputs must not
change during the high time of the CLRTXERR input.
3.3 PACKET RECEPTION PER PORT
Each port within the chip continuously monitors the net-
work. When activity is recognized via the Carrier Sense
(CSN) signal in 10 Mbit/sec Serial Mode, or through the
Receive Data Valid (RX_DV) signal in MII mode, the port
will then synchronize itself to the incoming data stream
through recognition of the Start Frame Delimiter (SFD) at
the end of Preamble. The destination address field of the
frame s then examined. Depending on the Address Match
Mode specified, the port will either recognize the frame as
being addressed to tself n a general or specific fashion or
abort the frame reception. The port can also be pro-
grammed to count all collisions on the network it's con-
nected to.
3.3.1 Preamble Processing
A port recognizes activity on the Ethernet via its Carrier
Sense line in 10 Mbit/sec Serial Mode or through its
Receive Data Valid ine n MII mode. In 10 MBit/sec Serial
Mode the end of preamble is detected by a double 1 serial
receive data pattern preceded by 6 bits of alternating 1’s
and 0’s. In MII mode the end of preamble s recognized by
the following nibble pattern:
Logic Values
0
1
1
1
0
0
1
1
RXD3
RXD2
RXD1
RXD0
In 10 MBit/sec Serial Mode, detection of a double 0 pattern
16 bit times after CSN goes high and before a proper Start
Frame Delimiter pattern is received will prevent reception
of the packet by the receiver. In MII mode, when RX_DV
goes high the RXD[3:0] lines must be driven with at least
1 byte of proper SFD pattern.
3.3.2 Address Matching
Ethernet addresses consist of two 6-byte fields. The first
bit of the address signifies whether it is a Station Address
or a Multicast/Broadcast Address.
Multicast Address:
If the first bit of the incoming
address is a 1 and the port is programmed to accept
Multicast Addresses without using Hash filtering, the
frame is received. A port also can be programmed to
use the hash filter for determining acceptance of
multicast addresses.
Broadcast Address:
The six incoming destination
address bytes must all be FF hex. If a port is
programmed to accept Broadcast or Multicast Ad-
dresses the frame will be received.
First Bit
0
1
Address
Station Address (Physical)
Multicast/Broadcast Address
(logical)
FCS Bits
3
4
Bit Selected
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
FCS Bits
0
1
Byte Selected
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Address matching occurs as follows:
Station Address:
All destination address bytes must
match the corresponding bytes found in the Station
Address Register. If Group Address mode s enabled,
the last 4 bits of the station address are masked out
during address matching.
After computing the FCS on the first six bytes of the
address field (Destination address), a port uses bits 0
thru 5 as an address to its Multi-cast address filter
register. Bit 0 of the FCS is assumed to be where
receive data enters the FCS generation circuitry. If
the corresponding bit addressed in the Multicast ad-
dress filter register is a ‘1’ the port will receive the
frame, otherwise t will discard the frame. Addressing
of the Multicast address filter register occurs using
bits 0 thru 2 to determine which byte is selected and
bits 3 thru 5 to determine which bit according to the
following tables:
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