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參數(shù)資料
| 型號： | 84C300A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（四端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 31/56頁 |
| 文件大?。?/td> | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-31
MD400152/E
Configuration Register #2
Allows for control of a port’s transmission of one packet at
a time, Busmode, Multi-cast hash filter, reception of runt
frames, and halting new transmissions until one of the
port’s transmit status registers is cleared.
Mode A: Don’t Load Tx Status Upon Successful
Transmit Mode
If bit #0 of configuration register #2 is set, then a
packet that has been transmitted successfully will not
have it’s status loaded into either of the two internal
transmit status registers.
Mode B: Disable Further Transmission Upon Full
Tx Status Register Mode
If bit #1 of configuration register #2 is set, whenever
both Tx Status Registers have been filled, no new
transmissions will occur until one of the Tx Status
Registers is cleared, even if the transmit FIFO has
transmit data.
Mode C: EOF on Data
This function puts a HIGH EOF value on both the last
double word of data and the status double word.
Mode D: Multicast Mode
Each port has a 64 bit multicast address filter register
which can be accessed as shown in the Internal Port
Register Addressing Table 3.6.1 on page 23. When
a port is programmed to receive multicast frames
(match mode 3), after computing the CRC on the
address field of the receiving frame (first 6 bytes), it
7
6
5
4
3
2
1
0
Bit
0
Value
‘1’
Definition
Disables loads to the transmit
status register upon a successful
transmission.
Disables new transmissions upon a
full transmit status register condition.
Generates an EOF on both the last
double word of data and also the
status double word.
Enables the hash filter for
multicast operation.
R/W
R/W
Default
0
Mode
A
1
‘1’
R/W
0
B
2
‘1’
R/W
0
C
3
‘1’
R/W
0
D
4
‘1’
Enables the reception of packets
without a discard even if the
RXABORTgoes high during the
reception of a packet.
Packs only two bytes
into the first double
word written to the
Receive FIFO.
[1]
Normal mode.
[2]
SQE Test Pass
SQE Test Fail
[4]
When this bit is SET, the TXRDY
is driven low after an EOF is
written into the transmit FIFO and
stays low until the packet is
successfully transmitted.
Sets the chip into Big Endian Mode
R/W
0
E
5
[3]
‘1’
W only
0
F1
‘0’
‘1’
‘0’
‘1’
R only
0
F2
6
R/W
0
G
7
‘1’
R/W
0
H
Configuration Register #2
Notes:
1. Non-Bidirectional Byte Enable Mode only.
2. Must be used for Bidirectional Byte Enable Mode.
3. This bit address is shared for two functions.
4. Read will clear this bit to ‘0’.
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