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參數(shù)資料
| 型號： | 84C300A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（四端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 22/56頁 |
| 文件大?。?/td> | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-22
MD400152/E
signals. Valid combinations of the RXTXBE inputs for
transmit FIFO writes are given below:
RXTXBE3
RXTXBE2
RXTXBE1
RXTXBE0
0
1
0
1
1
0
1
1
1
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
1
0
1
1
1
The TXRDY output for the port being read will remain high
until the port's transmit FIFO no onger has enough double
word space to meet the programmed threshold value.
The transmit and the receive FIFO are 128 bytes deep
organized as double word (32 bits) rows. During writes to
the transmit FIFO, the FIFO pointer gets incremented on
every write to the FIFO, rrespective of whether all the four
byte enables are asserted or not. Hence, during non
double word writes to the FIFO, one entire row of the FIFO
gets filled irrespective of whether all the bytes are valid or
not. The 84C300A automatically ignores the invalid bytes
when the data gets transmitted from the FIFO.
While transmit FIFO writes are occurring the SPDTAVL
output will remain high until the highgoing edge of the write
to the second to the last remaining double word space in
the FIFO. Because transmit FIFO writes are pipelined,
there will always be one more internal FIFO write after
TXWREN is deasserted.
Effect of Auto Retransmission Upon TXRDY
Behavior
As a packet s read out of a port’s Transmit FIFO by he
transmitter for transmission onto the network, the
corresponding TXRDY signal will not reflect any
reads that have occurred to the FIFO until enough
bytes of data have been transmitted to get past the
normal collision window of less than 64 byte times.
This means hat f a port’s TXRDY goes ow during he
writing of a packet to the Transmit FIFO, it will not go
HIGH again until both of the following conditions are
true:
1. The packet has been completely transmitted or
to a point 64 byte times from the beginning of the
transmission has been reached.
2. The number of bytes taken out of the transmit
FIFO for transmission subtracted from the
number of bytes written to the FIFO leaves the
FIFO with enough double word space avail
able to meet the threshold setting.
It is important to note that until the packet is com-
pletely transmitted or until enough of the packet is
transmitted to get past the normal collision window,
the TXRDY output will only reflect how many writes
have occurred and will not reflect how much of the
FIFO data has been read out for transmission. Be-
cause of this, it is important to insure enough packet
data has been written to prevent FIFO underflows if
there exists a large latency between the TXRDY
output being determined HIGH and he writing of more
data to the FIFO.
3.5.3 Receive FIFO Interface
To determine f the receive FIFO has reached ts threshold
number of double words of data, he RXRDY output can be
enabled by driving the RXINTEN input low. The RXRDY
output for the chip will be high under one of the following
conditions:
1. There are enough double words of data in the
channel's receive FIFO to meet or exceed the
programmed threshold value.
2. The status double word for a receive packet with
an end of rame value of HIGH s n he receive FIFO.
Once the RXRDY output is determined to be high, the
receive FIFO can be read. To read rom he Receive FIFO,
the RXRDEN and RXINTEN inputs must be asserted low
and the RXTXBE byte enables must be low for each read
cycle. Similar to the Transmit FIFO interface, all of the
above Receive FIFO interface control signals are clocked
into the chip on the high going edge of the RXRD_TXWR
clock input which also acts as the FIFO read strobe.
Because of this pipe lining the actual FIFO read will occur
one RXRD_TXWR cycle after the assertion of the Receive
FIFO interface control signals.
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