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參數(shù)資料
| 型號： | 84C300A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（四端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 25/56頁 |
| 文件大?。?/td> | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-25
MD400152/E
and indicating whether the address is physical or logical.
Bit 7 of station address byte 5 is compared to the last bit of
the received destination address. The Station Address
should be programmed prior to enabling a port’s receiver.
3.6.3 Transmit Command Register
The transmit command register is an 8 bit register. Bits 0
through 3 of the Transmit Command Register function as
interrupt mask bits, which provide for control of the condi-
tions allowed to generate transmit interrupts. Each of the
four bits may be individually set or cleared. When set, the
occurrence of the associated condition will cause an
interrupt to be generated. The four specific conditions for
which interrupts may be generated are:
1. A Transmit FIFO underflow occurred while
transmitting the packet.
2. A collision occurred while transmitting the packet.
3. A transmit error condition occurred i.e,
(Carrier sense never went active during
transmission or went rom an active o nactive state
during transmission or 16 collisions occurred for a
transmit packet or a late collision occurred).
4. The packet was transmitted successfully.
Interrupts are cleared by following the procedure given in
the section entitled "Clearing Interrupts" in section 3.3.5.
7
6
5
4
3
2
1
0
Bit
Value
Definition
R/W
Default Values
After Reset
0
‘1’
Generates an interrupt on the
occurrence of a transmit underflow.
W
0
1
‘1’
Generates an interrupt on the
occurrence of a collision during
the transmission of a packet.
W
0
2
‘1’
Generates an interrupt on the
occurrence of a transmit error
condition.
W
0
3
‘1’
Generates an interrupt on the
occurrence of a successful
transmission.
W
0
4
‘1’
Sets the chip into the MII mode
W
0
5
‘1’
Register
Code Bit
0.
These two bits are
used in conjunction
with the A[3:0]
address pins to access
registers other than the
Receive and Transmit
command registers
within a port.
W
0
6
‘1’
Register
Code Bit
1.
W
0
7
‘0’
Test Mode.
Note: This bit should not be
written HIGH under normal
circumstances.
W
0
Transmit Command Register Format
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