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參數(shù)資料
| 型號(hào)： | 84C300A |
| 廠商： | LSI Corporation |
| 英文描述： | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 中文描述： | 4端口快速以太網(wǎng)控制器（四端口快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 523K |
| 代理商： | 84C300A |
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84C300A 4-Port
Fast Ethernet Controller
4-19
MD400152/E
If the ncoming frame s addressed to a port n the chip
specifically (Destination Address matches the con-
tents of the Station Address Register), or s of general
or group interest (Broadcast or Multicast Address),
the port will pass the frame exclusive of Preamble and
FCS to the CPU buffer and indicate any error condi-
tions at the end of the frame. If, however, the address
does not match, as soon as the mismatch is recog-
nized, the port will terminate reception and issue an
RxDC.
A port may be programmed via the Match Mode bits
of the Receive Command Register to ignore all
frames (Disable Receiver), accept all rames (Promis-
cuous mode), accept frames with the proper Station
Address or the Broadcast Address (Station/Broad-
cast), or accept all frames with the proper Station
Address, the Broadcast Address, or all Multicast
Addresses (Station/Broadcast/Multicast).
3.3.3 Terminating Reception
Reception is terminated when either of the following con-
ditions occur:
Carrier Sense or Receive Data Valid Inactive:
Indicates that traffic is no longer present on the
Ethernet cable.
Overflow:
The host node for some reason is not able
to empty a port Receive FIFO as rapidly as it is filled,
and an error occurs as frame data s ost. On average
a port’s Receive FIFO must be serviced every 3200 ns
for 10 Mbit Ethernet or 320 ns for 100 Mbit Ethernet to
avoid this condition.
3.3.4 Using the RXABORT Pins to Terminate
Reception of a Packet
By pulsing the corresponding RXABORT pin high for a
minimum of 1 RXC cycle any time during the reception of
a packet, that particular port’s packet reception can be
terminated. When reception of a packet is terminated this
way, the Receive FIFO will be cleared and will stay cleared
until carrier sense in 10 MBit Serial Mode or Receive Data
Valid in MII mode, transitions from high to low or from low
to high ndicating either he end of he packet being aborted
or the beginning of a new receive packet. It s mportant to
note that RXABORT will cause the RXDC pin to go high
based on the conditions described under “Conditions that
cause the RXDC pin to go high”.
The RXDC signal s asserted so hat an external processor
will always have an indication of a packet abortion irre-
spective of whether it’s aborted by the user or by an
external PHY. However, the assertion of the RXDC signal
can be avoided by setting bit 4 of configuration register #2.
This will enable the reception of any packet irrespective of
errors and also reduce the number of signals (RXDC1_4
and CLRRXERR) that need to be processed when the
corresponding RXABORT goes high.
3.3.5 Receive Discard Conditions
Receive packets can be discarded for not meeting the
minimum IEEE 802.3 requirements for a good packet, for
address mismatches when the chip is not in promiscuous
mode, and by either user intervention or symbol errors
occurring from a 100 Mbit/sec physical device. n the case
of discards due to oversized packets, address mis-
matches, or the assertion of the RXABORT pin during
packet reception, further writing of receive packet data to
the receive FIFO is halted once the mismatch, receive
abort or oversized packet condition is determined.
Except for discards due to address mismatches, all packet
discards occur after carrier sense, or Receive Data Valid
in MII mode, deasserts. The discarding of receive packets
for error conditions can be controlled through bits 0
through 3 of he receive command register, and hrough bit
4 of configuration register #2. Listed below are the
required conditions for a receive discard to be produced:
1. Bit 0 of the Rx command register is LOW and a
receive FIFO overflow occurred during reception.
2. Bit 1 of the Rx command register is LOW and a
packet with a CRC error was received.
3. Bit 4 of Configuration register 2 is LOW and the
RXABORT pin is driven high while CSN is high.
4. Bit 3 of he Rx command register s LOW and a packet
with less than 64 bytes of data was received.
5. Bit 4 of the Rx command register is LOW and a
packet of size greater than 1518 was received.
6. The Receiver is not in promiscuous mode and a
address mismatch occurs.
Discarding of a receive packet by a port will cause any
packet data that was written to that receive FIFO to be
flushed from the FIFO. If no completely received packets
are in the receive FIFO at the time a receive discard
occurs, the receive FIFO will be completely flushed of
data. If however, a completely received packet, as indi-
cated by the packets status double word having been
written to the FIFO, is in the receive FIFO at the time of a
receive discard, the FIFO will be flushed only up to the ast
completely received packet. To prevent a receive packet
from being discarded due to an error condition, you can
selectively enable the reception of errored packets as
described n the section describing bit settings on configu-
ration register #2.
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