參數(shù)資料
型號： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 89/137頁
文件大?。?/td> 2145K
代理商： 7641
88
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
Notes 1:
Test conditions: I
OHL
=
±
5mA, C
L
= 50 pF
2:
t
wL
(RD) = ((n + 0.5) tc(PHI)) – 5 ns (n = wait number)
t
wL
(WR) = ((n + 0.5) tc(PHI)) – 5 ns (n = wait number)
For example, two software waits, PHI = 12 MHz operating
t
wL
(RD) = 2.5 tc(PHI) – 5 ns = 203.33 ns
Table 18 Recommended operating conditions
(Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Power source voltage
Analog reference voltage
Power source voltage
Analog reference voltage
DC-DC converter voltage
“H” input voltage
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
P2
0
–P2
7
RESET, X
IN
, X
CIN
, CNVss
USB D+, USB D–
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
P2
0
–P2
7
RESET, X
IN
, X
CIN
, CNVss
USB D+, USB D–
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
“H” input voltage (Selecting VIHL level input)
“H” input voltage
“H” input voltage
“L” input voltage
“L” input voltage (Selecting VIHL level input)
“L” input voltage
“L” input voltage
“H” total peak output current
(
Note 1
)
“L” total peak output current
(
Note 1
)
“H” total average output current P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
(
Note 1
)
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
“L” total average output current P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
(
Note 1
)
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
“H” peak output current
(
Note 2
)
“L” peak output current
(
Note 2
)
“H” average output current
(
Note 3
)
“L” average output current
(
Note 3
)
Timer X input frequency (
Note 4
)
Timer Y input frequency (
Note 4
)
Main clock input frequency (
Notes 4, 5
)
Sub-clock input frequency (
Notes 4, 6
)
V
CC
AVcc
V
SS
AV
SS
Ext. Cap.
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
Σ
I
OH(peak)
Σ
I
OL(peak)
Σ
I
OH(avg)
Σ
I
OL(avg)
I
OH(peak)
I
OL(peak)
I
OH(avg)
I
OL(avg)
f(CNTR
0
)
f(CNTR
1
)
f(X
IN
)
f(X
CIN
)
Limits
Typ.
3.3
3.3
0
0
3.3
V
V
V
V
V
Parameter
Min.
3.0
3.0
3.0
0.8V
CC
0.5V
CC
0.8V
CC
2.0
0
Max.
3.6
V
CC
Symbol
Unit
3.6
V
CC
Recommended Operating Conditions
In Vcc = 3 V
0
0
1
V
CC
V
CC
0.2V
CC
0.16V
CC
0.2V
CC
0.8
–80
80
–40
40
–10
10
–5.0
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
32.768
5.0
5.0
5.0
24
50/5.0
MHz
MHz
MHz
kHz/MHz
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