參數(shù)資料
型號(hào)： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁(yè)數(shù)： 40/137頁(yè)
文件大?。?/td> 2145K
代理商： 7641
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39
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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f
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(
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h
2
a
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o
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g
i
s
t
e
r
2
(
a
d
d
r
e
s
s
0
0
4
1
1
6
)
DMAC channel 1 hardware transfer request source bits
(D1HR)
b3b2b1b0
0 0 0 0: Not used
0 0 0 1: UART2 receive interrupt
0 0 1 0: UART2 transmit interrupt
0 0 1 1: Timer X interrupt
0 1 0 0: INT
1
interrupt
0 1 0 1: USB endpoint 1 IN_PKT_RDY signal
(falling edge active)
0 1 1 0: USB endpoint 2 IN_PKT_RDY signal
(falling edge active)
0 1 1 1: USB endpoint 4 IN_PKT_RDY signal
(falling edge active)
1 0 0 0: USB endpoint 1 OUT_PKT_RDY signal
(rising edge active)
1 0 0 1: USB endpoint 1 OUT_FIFO_NOT_EMPTY signal
(rising edge active)
1 0 1 0: USB endpoint 2 OUT_PKT_RDY signal
(rising edge active)
1 0 1 1: USB endpoint 4 OUT_PKT_RDY signal
(rising edge active)
1 1 0 0: Master CPU bus interface OBE
1
signal
(rising edge active)
1 1 0 1: Master CPU bus interface IBF
1
signal, data
(rising edge active)
1 1 1 0: Timer 1 trasmit/receive interrupt
1 1 1 1: CNTR
0
interrupt
DMAC channel 1 software transfer trigger (D1SWT)
0: No action (Bit is always read as
“
0
”
)
1: Request of channel 0 transfer by writing
“
1
”
(
Note 1
)
DMAC channel 1 USB and master CPU bus interface enable
bit (D1UMIE)
0: Disabled
1: Enabled
DMAC channel 1 transfer initiation source capture register
reset bit (D1CRR)
0: No action (Bit is always read as
“
0
”
)
1: Reset of channel 1 capture register by writing
“
1
”
(
Note 1
)
DMAC channel 1 enable bit (D1CEN)
0: Channel 0 disabled
1: Channel 0 enabled (
Note 2
)
D
D
M
M
A
A
C
1
c
M
h
2
a
n
n
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l
1
m
o
d
e
r
e
g
i
s
t
e
r
2
(
a
d
d
r
e
s
s
0
0
4
1
1
6
)
b
0
b
7
b0
b
7
b0
b7
b0
b7
N
o
t
e
s
1
:
2
:
T
W
h
h
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s
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n
b
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t
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u
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t
o
t
m
h
a
s
t
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c
i
a
t
l
l
y
“
c
1
l
e
”
,
a
s
r
e
i
m
d
t
l
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t
a
“
n
0
e
”
o
a
u
f
t
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l
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h
g
e
“
D
1
”
M
.
i
t
o
u
y
e
A
C
c
h
a
n
n
e
l
x
t
r
a
n
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f
e
r
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n
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t
i
a
t
i
o
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s
o
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r
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c
a
p
t
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r
e
r
e
g
i
s
t
e
r
r
e
s
e
t
b
i
t
(
b
i
t
6
o
f
D
M
A
x
M
2
)
t
o
“
1
”
.
Fig. 32 Structure of DMACx related register
相關(guān)PDF資料
PDF描述
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
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