參數(shù)資料
型號(hào)： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 48/137頁
文件大?。?/td> 2145K
代理商： 7641
47
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
The USB suspend detect signal flag goes to
“
0
”
when the USB re-
sume signal detect flag (RESUME) is set to
“
1
”
. During suspend
mode, if the clock operation is started up with a process (remote
wake-up) other than the resume interrupt process (for example;
reset or timer), make sure to clear the USB suspend detect signal
flag to
“
0
”
when you set the USB remote wake-up bit to
“
1
”
. When
the USB FCU is in suspend mode and detects a non-idle signal on
the D+/D- line, the USB resume detect flag and the USB resume
signal interrupt status flag both go to
“
1
”
and a resume interrupt
request occurs. At this point, pull the internal registers (A, X, Y) in
this interrupt process routine. Take the following procedure in the
USB resume interrupt process.
(1) Set the USB line driver current control bit to
“
0
”
. (When operat-
ing at Vcc = 3.3 V, this bit does not need to be set.)
(2) Set the frequency synthesizer enable bit to
“
1
”
and set a 2 ms
to 5 ms wait.
(3) Check the frequency synthesizer lock status bit. If
“
0
”
, it must
be checked again after a 0.1 ms wait.
(4) Enable the USB clock.
Fig. 37 Structure of USB control register
USB control register (address 0013
16
)
USBC
Reserved bit (
“
0
”
at read/write)
USB default state selection bit (USBC1)
0: In default state after power-on/reset
1: In default state after USB reset signal received
USB artificial SOF enable bit (USBC2)
0: Artificial SOF disabled
1: Artificial SOF enabled
USB line driver current control bit (USBC3)
0: High current mode
1: Low current mode
USB line driver supply enable bit (USBC4) (
Note 1
)
0: Line driver disabled
1: Line driver enabled
USB clock enable bit (USBC5)
0: 48 MHz clock to the USB block disabled
1: 48 MHz clock to the USB block enabled
USB SOF port select bit (USBC6)
0: SOF output disabled
1: SOF output enabled
USB enable bit (USBC7)
0: USB block disabled (
Note 2
)
1: USB block enabled
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7
Set the USB resume signal interrupt status flag to
“
0
”
after the
wake-up sequence process. The USB resume detect flag goes to
“
0
”
at the same time. When the clock operation is started up with
a remote wake-up, set the USB remote wake-up bit to
“
1
”
after the
wake-up sequence process. (keep it set to
“
1
”
for a minimum of 10
ms and maximum of 15 ms). By doing this, the MCU will send a
resume signal to the host CPU and let it know that the suspend
state has been released.
After that, set the USB remote wake-up bit and the USB suspend
detection flag to
“
0
”
, because the USB suspend detection flag is
not automatically cleared to
“
0
”
with a remote wake-up.
[USB Control Register] USBC
When using the USB function, the USB enable bit must be set to
“
1
”
. The USB line driver supply bit must be set to
“
0
”
(DC-DC con-
verter is disabled) when operating at Vcc = 3.3V. In this condition,
the setting of the USB line driver current control bit has no effect
on USB operations.
When the USB artificial SOF enable bit is set to
“
1
”
, the MCU
judges that a SOF packet is received within 250 ns from a frame
starting if an SOF packet is destroyed owing to some cause.
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