參數(shù)資料
型號： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 12/137頁
文件大小： 2145K
代理商： 7641
11
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
[CPU Mode Registers A, B (CPUMA, CPUMB)] 0000
16
, 0001
16
The CPU mode register contains the stack page select bit and the
CPU operating mode select bit and so on.
The CPU mode registers are allocated at address 0000
16
, 0001
16
.
Fig. 8 Structure of CPU mode register
I
Notes
Do not use the microprocessor mode in the flash memory version.
CPU mode register A (address 0000
16
)
CPMA
P
r
o
c
e
s
s
o
r
m
o
d
e
b
i
t
s
b
0
0
1
1
t
a
0
1
i
x
u
0
1
a
0
1
n
t
0
1
E
x
0
1
1
b
0
1
0
1
c
:
:
t
b
:
:
i
n
:
:
e
:
:
t
e
:
:
0
:
:
:
:
k
P
P
o
-
c
S
O
O
S
r
n
E
f
S
r
X
I
X
C
S
M
M
N
p
a
a
“
l
o
t
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s
c
s
t
o
a
x
Y
n
N
-
i
n
e
i
c
o
a
g
e
g
e
1
c
p
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c
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g
”
.
k
p
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p
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e
0
1
-
r
c
y
r
a
s
h
e
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l
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p
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d
s
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e
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n
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d
m
e
o
d
(
N
e
o
o
t
e
1
)
S
e
b
i
t
F
S
e
a
k
a
e
(
X
C
d
t
i
n
(
X
I
t
i
n
d
s
t
e
a
l
I
N
-
X
C
O
U
T
)
c
o
n
t
r
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l
b
i
t
g
M
N
-
g
X
O
U
T
)
c
o
n
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l
b
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I
m
c
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c
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c
(
k
X
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N
-
e
X
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c
U
t
T
b
i
o
t
r
(
N
X
C
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t
I
N
-
e
X
C
2
)
o
O
U
T
)
c
l
o
U
c
T
k
s
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c
t
b
i
t
X
O
N
-
I
X
C
O
U
T
b0
b7
1
Notes 1:
This is not available in the flash memory version.
2:
When (CPMA 6, 7) = (0, 0), the internal system clock can be selected
between f(X
IN
) or f(X
IN
)/2 by CCR7.
The internal clock
φ
is the internal system clock divided by 2.
0
b
7
CPU mode register B (address 0001
16
)
CPMB
Slow memory wait select bits
b1b0
0 0: No wait
0 1: One-time wait
1 0: Two-time wait
1 1: Three-time wait
Slow memory wait mode select bits
b3b2
0 0: Software wait
0 1: Not available
1 0: RDY wait
1 1: Software wait plus RDY input anytime wait
Expanded data memory access bit
0: EDMA output disabled
1: EDMA output enabled
HOLD function enable bit
0: HOLD function disabled
1: HOLD function enabled
Resereved bit (
“
0
”
at read/write)
Fix to
“
1
”
.
b
1 0
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