參數(shù)資料
型號： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 24/137頁
文件大小： 2145K
代理商： 7641
23
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by applying
“
L
”
level to any
pin of port P2 that have been set to input mode. In other words, it is
generated when AND of input level goes from
“
1
”
to
“
0
”
. An example
of using a key input interrupt is shown in Figure 18, where an inter-
rupt request is generated by pressing one of the keys consisted as
an active-low key matrix which inputs to ports P2
0
–
P2
4
.
Fig. 18 Connection example when using key input interrupt and port P2 block diagram
P
l
a
o
r
t
h
P
2
7
t
c
P
d
o
i
r
e
t
c
P
t
i
2
7
o
r
n
r
e
g
i
s
t
e
r
=
“
1
”
P
2
7
o
u
t
p
u
t
P
B
o
r
t
7
P
=
2
p
0
u
”
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
i
t
“
Port PXx
“
L
”
level output
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
F
a
l
l
e
i
n
t
g
e
c
e
t
d
o
g
r
e
d
P2
6
output
P
2
5
o
u
t
p
u
t
P2
4
input
P
2
3
i
n
p
u
t
P
2
2
i
n
p
u
t
P
2
1
i
n
p
u
t
P
2
0
i
n
p
u
t
P
l
a
o
r
t
h
P
2
6
t
c
Port P2
6
direction register =
“
1
”
P
B
o
r
t
6
P
=
2
p
0
u
”
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
i
t
“
F
a
l
l
e
i
n
t
g
e
c
e
t
d
o
g
r
e
d
P
l
a
o
r
t
h
P
2
5
t
c
Port P2
5
direction register =
“
1
”
P
B
o
r
t
5
P
=
2
p
0
u
”
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
i
t
“
F
a
l
l
e
i
n
t
g
e
c
e
t
d
o
g
r
e
d
P
l
a
o
r
t
h
P
2
4
t
c
P
d
o
i
r
e
t
c
P
t
i
2
4
o
r
n
r
e
g
i
s
t
e
r
=
“
0
”
P
B
o
r
t
4
P
=
2
p
0
u
”
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
i
t
“
F
a
l
l
e
i
n
t
g
e
c
e
t
d
o
g
r
e
d
P
l
a
o
r
t
h
P
2
3
t
c
P
d
o
i
r
e
t
c
P
t
i
2
3
o
r
n
r
e
g
i
s
t
e
r
=
“
0
”
Port P2 pull-up control register
Bit 3 =
“
0
”
F
a
l
l
e
i
n
t
g
e
c
e
t
d
o
g
r
e
d
Port P2
2
latch
Port P2
2
direction register =
“
0
”
Port P2 pull-up control register
Bit 2 =
“
0
”
F
a
l
l
e
i
n
t
g
e
c
e
t
d
o
g
r
e
d
Port P2
1
latch
P
d
o
i
r
e
t
c
P
t
i
2
1
o
r
n
r
e
g
i
s
t
e
r
=
“
0
”
P
B
o
r
t
1
P
=
2
p
0
u
”
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
i
t
“
Falling edge
detector
P
l
a
o
r
t
h
P
2
0
t
c
P
B
o
r
t
0
P
=
2
p
0
u
”
l
l
-
u
p
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
o
d
i
i
t
“
F
a
l
l
e
i
n
t
g
e
c
e
t
d
o
g
r
e
d
P
r
e
t
c
P
t
2
0
o
r
i
n
r
e
g
i
s
t
e
r
=
“
0
”
Port P2
Input reading circuit
P-channel transistor for pull-up
CMOS output buffer
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