參數(shù)資料
型號(hào)： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁(yè)數(shù)： 74/137頁(yè)
文件大?。?/td> 2145K
代理商： 7641
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73
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
N
o
t
e
s
Reset
C
P
M
A
4
“
1
”
←
→
“
0
”
F
“
S
0
C
0
→
“
”
←
1
”
X
I
X
C
F
r
c
l
C
N
I
e
o
P
c
l
c
u
k
M
o
c
o
n
t
o
=
k
c
c
k
y
p
0
o
s
s
s
p
C
c
t
y
e
,
i
l
l
a
p
t
h
t
i
e
e
n
d
s
g
,
,
N
q
c
l
o
p
n
,
F
e
s
i
z
e
r
A
d
S
C
=
6
0
φ
=
f
(
X
I
N
/
4
)
1 :
Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 :
In Stop mode, though the frequency synthesizer is not automatically disabled, the oscillator which sends clocks to the frequency
synthesizer stops. Set the system clock and disable the frequency synthesizer before execution of the STP instruction.
3 :
φ
= f(X
IN
)/2 can be also used by setting the X
IN
divider select bit (CCR7) to
“
1
”
. Then this diagram also applies to that case.
4 :
The frequency synthesizer
’
s input can be selected between X
IN
input and X
CIN
input regardless of the system clock. This diagram
assumes the frequency synthesizer
’
s input to be the system clock. Enable the oscillator to be used for the frequency synthesizer
’
s input
before enabling the frequency synthesizer.
5 :
Select the X
CIN
input as the frequency synthesizer
’
s input by setting the frequency synthesizer input bit (FSC3) to
“
1
”
before stopping X
IN
oscillation.
(N
o
t
e
3
)
X
I
X
C
F
r
c
l
C
N
I
e
o
P
c
l
c
u
k
M
o
c
o
n
s
=
k
c
c
c
k
y
i
l
0
o
s
s
s
l
a
C
c
t
y
t
i
,
i
l
l
a
p
t
h
g
S
t
i
e
e
n
d
s
g
,
,
N
q
c
l
o
p
n
n
F
e
o
i
z
e
r
A
,
C
=
4
1
φ
= f(X
IN
/4)
C
“
0
P
”
←
M
A
→
“
6
1
”
X
I
X
C
F
r
c
l
C
N
I
e
o
P
c
l
c
u
k
M
o
c
o
n
s
=
k
c
c
c
k
y
i
l
4
o
s
s
s
l
a
C
c
t
y
t
i
,
i
l
l
a
p
t
h
g
S
t
i
e
e
n
d
s
g
,
,
N
q
c
l
o
p
n
n
F
e
o
i
z
e
r
A
,
C
=
4
1
φ
= f(PLL)/2
(Note 3)
(Note 4)
W
A
I
T
S
T
O
P
(N
o
t
e
2
)
W
A
I
T
F
“
S
0
C
0
→
“
”
←
1
”
X
IN
clock oscillating,
X
CIN
clock oscillating,
Frequency synthesizer
clock stopped,
CPMA = 1C, FSC = 60
φ
=
f
(
X
I
N
/
4
)
(N
o
t
e
3
)
X
IN
clock oscillating,
X
CIN
clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = 1C, FSC = 41
φ
= f(X
IN
/4)
C
“
0
P
”
←
M
A
→
“
6
1
”
X
IN
clock oscillating,
X
CIN
clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = 5C, FSC = 41
φ
= f(PLL)/2
(Note 3)
(Note 4)
(Note 2)
W
A
I
T
STOP
W
A
I
T
C
P
M
A
7
“
1
”
←
→
“
0
”
FSC0
“
0
”
←→
“
1
”
X
I
X
C
F
r
c
l
C
N
I
e
o
P
c
l
c
u
k
M
o
c
o
n
t
o
=
k
c
c
k
y
p
9
o
s
o
s
p
C
c
s
y
d
,
i
c
n
,
F
l
l
a
i
l
t
t
a
h
i
n
t
e
g
n
s
,
g
z
N
q
c
l
l
i
,
e
e
s
i
r
A
e
S
C
=
6
0
φ
= f(X
CIN
/2)
X
I
X
C
F
r
c
l
C
N
I
e
o
P
c
l
c
u
k
M
o
c
o
n
s
=
k
c
c
c
k
y
i
l
9
o
s
o
s
l
a
C
c
s
y
t
i
,
i
c
n
n
F
l
l
a
i
l
t
g
S
t
a
h
,
C
i
n
t
e
g
n
s
(Note 4)
,
g
z
N
q
c
l
l
i
,
e
e
o
i
r
A
=
4
1
φ
= f(X
CIN
/2)
CPMA6
“
0
”
←→
“
1
”
X
I
X
C
F
r
c
l
C
N
I
e
o
P
c
l
c
u
k
M
o
c
o
n
s
=
k
c
c
c
k
y
i
l
D
o
s
o
s
l
a
C
c
s
y
t
i
,
i
c
n
n
F
l
l
a
i
l
t
g
S
t
a
h
,
i
n
t
e
g
n
s
,
g
z
N
q
c
l
l
i
,
e
e
o
i
r
A
C
=
4
1
φ
= f(PLL)/2
(Note 2)
O
P
WAIT
S
T
W
A
I
T
C
P
M
A
5
“
1
”
←
→
“
0
”
F
“
S
0
C
0
→
“
”
←
1
”
X
I
X
C
F
r
c
l
C
N
I
e
o
P
c
l
c
u
k
M
o
c
o
n
t
o
=
k
c
c
k
y
p
B
s
t
o
s
p
C
o
p
s
y
e
d
,
p
c
n
,
F
e
l
l
t
h
d
a
e
,
i
s
N
q
c
l
i
t
n
g
z
,
e
e
s
i
r
A
S
C
=
6
8
φ
=
f
(
X
CI
N
/
2
)
X
I
X
C
F
r
c
l
C
N
I
e
o
P
c
l
c
u
k
M
o
c
o
n
s
=
k
c
c
c
k
y
i
l
B
s
t
o
s
l
a
C
o
p
s
y
t
i
,
p
c
n
n
F
e
l
l
t
h
g
S
d
a
e
,
C
,
i
s
N
q
c
l
i
t
n
g
z
,
e
e
o
i
r
A
=
4
9
φ
= f(X
CIN
/2)
C
“
0
P
”
←
M
A
→
“
6
1
”
X
I
X
C
F
r
c
l
C
N
I
e
o
P
c
l
c
u
k
M
o
c
o
n
s
=
k
c
c
c
k
y
i
l
F
s
t
o
s
l
a
C
o
p
s
y
t
i
,
p
c
n
n
F
e
l
l
t
h
g
S
d
a
e
,
C
,
i
s
N
q
c
l
i
t
n
g
z
,
e
e
o
i
r
A
=
4
9
φ
= f(PLL)/2
(N
P
o
t
e
2
)
WAIT
S
T
O
W
A
I
T
(Note 5)
(Note 4)
Remarks :
This diagram assumes that:
Stack page is page 1
In single-chip mode
(Depending on the CPU mode register A)
φ
expresses the internal clock.
Fig. 68 State transitions of clock
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