參數(shù)資料
型號: 7641
英文描述: 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述: 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù): 35/137頁
文件大?。?/td> 2145K
代理商: 7641
34
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
UTXD output (P8
4
/UTXD
1
,
P8
0
/UTXD
2
/SRDY)
r
a
n
s
m
i
t
c
D
0
D
1
SP
ST
D
2
D
3
D
4
D
5
D
6
D
7
P
SP
T
r
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n
s
f
e
r
c
l
o
c
k
T
r
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n
m
i
t
e
n
a
b
l
e
b
i
t
T
r
a
n
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e
m
m
i
t
p
b
t
y
u
f
l
f
a
e
r
f
g
T
o
m
p
l
e
t
e
f
l
a
g
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
D
0
D
1
ST
D
a
t
a
s
e
t
i
n
t
o
U
A
R
T
x
t
r
a
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m
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b
u
f
f
e
r
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r
1
Data transferring from UARTx transmit
buffer register 1 to Transmit shift register 1
This timing applies to the conditions:
Character length = 8 bits
Parity enabled
1 stop bit
RTS (Request-to-Send) Function
As a receiver, the UART can be configured to generate the Re-
quest-to-Send (RTSx) handshaking signal. This is enabled by
setting the RTS Function Enable Bit (bit 6 of UxCON) to
1
.
When reception is enabled, that is the Receive Enable Bit is
1
,
the RTSx pin goes
L
to inform a transmitter that reception is pos-
sible. The RTSx pin goes
H
at reception starting and does
L
at
receiving of the last bit.
The delay time from the reception of the last stop bit to the asser-
tion of RTSx is selectable using the RTS Assertion Delay Count
Select Bits.
BRGx (x = 1, 2)
count source
D
0
URXD (P8
5
/URXD
1
,
P8
1
/URXD
2
/SCLK)
ST
SP
D
1
D
7
RTSx pin (P8
7
/RTS
1
,
P8
3
/RTS
2
/STXD)
Receive enable bit
Receive buffer
empty flag
Transfer clock
Transfer clock generated at falling edge
of start bit and receive started
Receive data latched
Data transferring from UARTx receive register
1 to Receive buffer register 1 (
Note
)
Note:
When no RTS assertion delay, the RTSx pin goes
L
.
The RTS assertion delay counts are selected by bits 4 to 7 of UARTx RTS control register.
This timing applies to the conditions:
Character length = 8 bits
Parity enabled
1 stop bit
Fig. 28 UARTx transmit timing (CTS function disbled)
When the Receive Enable Bit is set to
0
or the Receive initializa-
tion bit is set to
1
, the RTSx pin goes
H
. Even when the
Receive Enable Bit is set to
1
, the RTSx pin goes
H
if detecting
an invalid start bit.
Figure 29 shows the UARTx receive timing.
Fig. 29 UARTx transmit timing (RTS function enabled)
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