參數(shù)資料
型號: 7641
英文描述: 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述: 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù): 121/137頁
文件大小: 2145K
代理商: 7641
120
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 100 Timing for clear status register
G
Clear Status Register Command
This command clears the bits (SR3 to SR5) which are set when
the status register operation ends in error. When the
50
16
com-
mand code is sent with the 1st byte, the aforementioned bits are
cleared. When the clear status register operation ends, the SRDY
(BUSY) signal changes from
H
to
L
level.
SCLK
SRXD
STXD
SRDY (BUSY)
50
16
A
B
8
A
B
1
t
5
o
A
B
1
A
6
t
o
B
2
3
4
1
1
6
d
a
t
a
0
d
a
t
a
2
5
5
S
C
L
K
S
R
X
D
S
T
X
D
S
R
D
Y
(
B
U
S
Y
)
G
Page Program Command
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page pro-
gram command as explained here following.
(1) Transfer the
41
16
command code with the 1st byte.
(2) Transfer addresses AB
8
to AB
15
and AB
16
to AB
23
with the 2nd
and 3rd bytes respectively.
(3) From the 4th byte onward, as write data (DB
0
to DB
7
) for the
page (256 bytes) specified with addresses A
8
to A
23
is input
sequentially from the smallest address first, that page is auto-
matically written.
When reception setup for the next 256 bytes ends, the SRDY
(BUSY) signal changes from
H
to
L
level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
Fig. 101 Timing for page program
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