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參數(shù)資料
| 型號： | ZR36506 |
| 英文描述： | Fast Recovery Rectifier Diodes |
| 中文描述： | 外圍芯片 |
| 文件頁數(shù)： | 83/99頁 |
| 文件大?。?/td> | 452K |
| 代理商： | ZR36506 |
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Zoran ZR 36506 USBV ision – Datasheet
Zoran Proprietary and Confidential
Programmable I / O Pins and 48 MHz Output Pin
13 -1
13 P
ROGRAMMABLE
I / O P
I NS AND
48 MH
Z
O
UTPUT
P
I N
The ZR36506 has two programmable I/O pins for general purpose usage. These are IO-1 and IO-
2 pins, which are Open-Drain.
Each of these pins - if used - must be connected to an external Pull-Up resistor to 3.3-5.0 V (if
not used, it can be tied to GND). The external Pull-Up resistor should be in the range of 1-10
K
.
To use these pins as inputs, the host computer should write '1' to the appropriate bit in the
IOPIN_REG register (in the ZR36506 register bank) - these are the IO_1 and IO_2 bits,
respectively. In this condition, the voltage level presented on the IO-1 or IO-2 pin may be read
by the host computer via the appropriate bit ('0' represents <0.8 V, '1' represents > 2.0 V).
To use these pins as outputs, the host computer should write the output value to the appropriate
bit in the IOPIN_REG register; In this condition, and assuming that no external device forces the
voltage level presented on the IO-1 or IO-2 pin, the written value will be reflected ('0' will
generate 0 V, '1' will generate 3.3-5.0 V).
Upon a Power On Reset or a USB-Reset operation, the IO-1 and IO-2 pins are cleared to '0'. In
Suspend mode, these pins are temporarily set to High-z.
The ZR36506 provides a 48 MHz clock output for SDRAM interface and general purpose usage.
The pin CLK48 is dedicated to this, and is enabled when the CLK48_EN bit is set to '1'
(Reg.0/d3). When disabled, the output level in this pin is constant '0'.
The 48 MHz output is 50% duty cycle with 1 nS jitter, and is derived from the external 12 MHz
crystal (an internal analog PLL is used).
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