參數(shù)資料
型號(hào)： ZR36506
英文描述： Fast Recovery Rectifier Diodes
中文描述： 外圍芯片
文件頁數(shù)： 43/99頁
文件大?。?/td> 452K
代理商： ZR36506
Zoran ZR 36506 USBV ision – Datasheet
Zoran Proprietary and Confidential
Video I nput I nterface
8 -1
8
V
I DEO
I
NPUT
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NTER FACE
The ZR36506 digital video input is in YUV format. The ZR36506 interface for this format is
flexible and supports 4:2:2 (8-bit, or 16-bit), and 4:1:1 timings (12-bit). Horizontal and vertical
controls may be physical pulses or coded signals. Additionally, pixel clock and pulse polarity of
the control signals may be programmed to either positive or negative.
All the input buffers in the ZR36506 that are supposed to be connected to the digital video
source are 5-volt tolerant. This means that a camera with 5-volt CMOS outputs will not cause
any damage to the ZR36506, even though the ZR36506 operating voltage is 3.3 Volts.
The ZR36506 digital video input consists of the following signals:
§
Y0-Y7
In the 4:2:2 16-bit, and 4:1:1 (12-bit) modes, this is the Luminance input bus. In the 4:2:2 8-
bit mode, this bus is used for mux YUV data. This bus is sampled by the VCLK input clock
for the unsigned binary value (0-255) of the Y component (or U and V as well in the 8-bit
mode).
§
U0-U7
This is the Color (U or U/V) input bus. In the 4:2:2 16-bit and 4:1:1 (12-bit) formats, this
bus is sampled by the even cycles of VCLK input clock for the binary value (0-255) of the
U component, and by the odd cycles of VCLK input clock for the binary value (0-255) of
the V component.
§
VSYNC
This is the Vertical Synchronization pulse, which indicates the start of a new video field (in
Interlaced mode) or the start of a new video frame (in Non-Interlaced mode). This pulse is
normally negative.
§
HSYNC
This is the Horizontal Synchronization pulse, which indicates the start of a new video line.
This pulse is normally negative.
§
FID
This signal is used in Interlaced mode, to indicate whether the current field is even or odd.
In Non-Interlaced mode, this input is ignored by the ZR36506.
§
VCLK
This signal is the video pixel clock. It is used by the ZR36506 to sample all other inputs in
the digital video interface.
§
HVALID
This input is the pixel valid qualifier. When inactive, the ZR36506 refers to the samples that
come from the Y, U, and V buses as blank pixels (which are not considered a part of the
digital image). The ZR36506 may be programmed to ignore the HVALID input.
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