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| 型號(hào)： | ZR36506 |
| 英文描述： | Fast Recovery Rectifier Diodes |
| 中文描述： | 外圍芯片 |
| 文件頁(yè)數(shù)： | 59/99頁(yè) |
| 文件大小： | 452K |
| 代理商： | ZR36506 |
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Zoran ZR 36506 USBV ision – Datasheet
Zoran Proprietary and Confidential
S DR AM Control and I nterface
9 -3
§
SDRAM Initialization
SDRAM requires initialization after Reset, Suspend and power down. Users should write 1
to register 18 (DRM_CONT) bit 1 of RBCS after these events, allowing the SDRAM at
least 100 microseconds to stabilize internal circuitry. The MAU then automatically performs
an SDRAM initialization sequence and allows other memory tasks to be performed. This
task lasts approximately 600 nS.
§
I n the beginning of every task, the MAU programs the
Mode Register, utilizing the address bus.
§
CAS Latency is alw ays set to 2, Burst type is alw ays
sequential, and Burst length is set to 8 for USB Fifo read
tasks and to Full-Page for all other tasks. Only the USB
Fifo read task employs Auto Precharge. All other tasks
( Read and W rite) perform a PALL command during task
command sequence.
The following table specifies the registers that are used to support SDRAM:
S DR AM and Memory Buffer S etup R eg isters
Register
Address
Register
Name
Function
Default
Value
18
DRM_CONT d0:
REF
'0' = 8.2 ms refresh rate.
'1' = 16 ms refresh rate.
d1:
d2:
SDRAM_EN.
RES_UR Restart video out buffer read
logic.
RES_FDL Restart video-frame-delay
logic.
d3:
d4:
RES_VDW Restart video out buffer
write logic.
d5-d7: reserved.
d0-d3: Bits 16 to 19 of FDL_LAST_WORD.
00H
19
DRM_PRM1
d4-d7: Reserved.
00H
20
DRM_PRM2
d0-d3: Bits 8 to 11 of FDL_1ST_LINE.
d4-d7: Reserved.
00H
21
DRM_PRM3
d0-d3: Bits 8 to 11 of VDW_1ST_LINE.
d4-d7: Bits 8 to 11 of VDW_LAST_LINE.
00H
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