參數(shù)資料
型號： ZR36506
英文描述： Fast Recovery Rectifier Diodes
中文描述： 外圍芯片
文件頁數(shù)： 57/99頁
文件大小： 452K
代理商： ZR36506
Zoran ZR 36506 USBV ision – Datasheet
Zoran Proprietary and Confidential
S DR AM Control and I nterface
9 -1
9
SDRAM C
ONTROL AND
I
NTER FACE
MAU ( Memory Access unit)
The MAU is responsible for all data transfers between the internal units and external SDRAM.
The SDRAM in use is organized as two Banks of 524,288-Word X 16 Bit and is accessible via a
16 Bit data bus. The design is based on 3.3 V powered SDRAMs manufactured by Micron
(MT48LC1M16A1) and Fujitsu (MB81F161622C). The SDRAM operation modes employed by
the MAU are:
§
Full-Page-Mode-Read
§
Full-Page-Mode-Write
§
Burst-of-8-Read
§
Auto Precharge Mode
§
Manual two Bank Precharge
§
CAS Latency = 2 to support SDRAMS that do not have CAS Latency = 1(also sufficient for
operating frequency of 48 MHz). Both 8.2 ms and 16 ms refresh rates are supported.
Refer to the following MAU main block diagram:
da [11:0]
cke
csn
rasn
casn
wen
URU
USB
Read
Unit
FDL
Frame
Delay
Line
VDW
Video
Data
Write
RFU
Refresh and
Initialization
Unit
DIB
DRAM
Interface
Block
DSM
DRAM
State
Machine
MAU
usb_dat_reg
pix_rst48n
clk48
rst48n
pwr_dwn
drm_cont
drm_prm
fdl_dat_req
vid_mem_req
frame_end_pre
frame_end
buf_state_idle_pre
buf_state_idle
buf_state_last_pre
buf_state_last
From CVI
From RBCS
From DVC
ur_fifo_wr
nextvf
next8w
vdw_buf_rd
vdw_el
eo8w
fdl_fifo_rd
fdl_fifo_wr
vdw_ret
dd [15:0]
C
D
S
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