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參數(shù)資料
| 型號： | XRT83VSH38IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA225 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225 |
| 文件頁數(shù)： | 66/76頁 |
| 文件大?。?/td> | 722K |
| 代理商： | XRT83VSH38IB |
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XRT83VSH38
63
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
T
ABLE
38: M
ICROPROCESSOR
R
EGISTER
0
X
81
H
, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
0
X
81
H
N
AME
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
D7
LCV_OF
Line Code Violation / Over Flow Select
0 = LCV_OFD monitors LCV activity
1 = LCV_OFD monitors OF activity
R/W
0
D6
CLKSEL2
Clock Select Inputs for Master Clock Synthesizer bit 2:
In
Host
mode, CLKSEL[2:0] are input signals to a programma-
ble frequency synthesizer that can be used to generate a mas-
ter clock from an external accurate clock source according to
the following table;
In
Hardware
mode, the state of these signals are ignored and
the master frequency PLL is controlled by the corresponding
Hardware
pins.
R/W
0
D5
CLKSEL1
Clock Select inputs for Master Clock Synthesizer bit 1:
See description of bit D6 for function of this bit.
R/W
0
D4
CLKSEL0
Clock Select inputs for Master Clock Synthesizer bit 0:
See description of bit D6 for function of this bit.
R/W
0
D3
MCLKRATE
Master clock Rate Select:
The state of this bit programs the
Master Clock Synthesizer to generate the T1/J1 or E1 clock.
The Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE =
“1”.
R/W
0
D2
RXMUTE
Receive Output Mute:
Writing a “1” to this bit, mutes receive
outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for
any channel that detects an RLOS condition.
N
OTE
:
RCLK is not muted.
R/W
0
D1
EXLOS
Extended LOS:
Writing a “1” to this bit extends the number of
zeros at the receive input of each channel before RLOS is
declared to 4096 bits. Writing a “0” reverts to the normal mode
(175+75 bits for T1 and 32 bits for E1).
R/W
0
D0
ICT
In-Circuit-Testing:
Writing a “1” to this bit configures all the
output pins of the chip in high impedance mode for In-Circuit-
Testing. Setting the ICT bit to “1” is equivalent to connecting
the
Hardware
ICT pin 88 to ground.
R/W
0
2048
2048
2048
1544
MCLKE1
kHz
2048
2048
1544
1544
MCLKT1
kHz
1544
1544
2048
1544
2048
CLKOUT/
kHz
1544
2048
1544
0
0
1
1
CLKSEL0
0
0
0
0
CLKSEL1
0
0
0
0
CLKSEL2
0
1
0
0
0
0
1544
2048
0
1
0
1
MCLKRATE
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT84L14 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT84L18 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT84L38 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT84L38_06 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT84L38IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83VSH38IB-F | 功能描述:外圍驅(qū)動器與原件 - PCI 8 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83VSH38IB-F | 制造商:Exar Corporation 功能描述:T1/E1 LIU IC |
| XRT84L38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER |
| XRT84L38_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER |
| XRT84L38IB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8 Ch T1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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