參數(shù)資料
型號: XRT83VSH38IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 30/76頁
文件大?。?/td> 722K
代理商: XRT83VSH38IB
XRT83VSH38
27
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
4.0
TRANSMIT PATH LINE INTERFACE
The transmit path of the XRT83VSH38 LIU consists of 8 independent T1/E1/J1 transmitters. The following
section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A
simplified block diagram of the transmit path is shown in
Figure 15
.
F
IGURE
15. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
P
ATH
4.1
TCLK/TPOS/TNEG Digital Inputs
In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has
no function and can be left unconnected. The XRT83VSH38 can be programmed to sample the inputs on
either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising
edge of TCLK, set TCLKE to "1" in the appropriate global register.
Figure 16
is a timing diagram of the
transmit input data sampled on the falling edge of TCLK.
Figure 17
is a timing diagram of the transmit input
data sampled on the rising edge of TCLK. The timing specifications are shown in
Table 6
.
F
IGURE
16. T
RANSMIT
D
ATA
S
AMPLED
ON
F
ALLING
E
DGE
OF
TCLK
F
IGURE
17. T
RANSMIT
D
ATA
S
AMPLED
ON
R
ISING
E
DGE
OF
TCLK
HDB3/B8ZS
Encoder
Tx Jitter
Attenuator
Timing
Control
Tx Pulse Shaper
& Pattern Gen
Line Driver
TTIP
TRING
TCLK
TPOS
TNEG
TCLK
TPOS
or
TNEG
TCLK
R
TCLK
F
T
HO
T
SU
TCLK
TPOS
or
TNEG
TCLK
F
TCLK
R
T
HO
T
SU
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