參數(shù)資料
型號: XRT83VSH38IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 60/76頁
文件大?。?/td> 722K
代理商: XRT83VSH38IB
XRT83VSH38
57
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
D4
LCV_OFD
Line Code Violation / Counter Overflow Detection
This bit serves a dual purpose. By default, this bit monitors the line
code violation activity. However, if bit 7 in register 0x81h is set to a
"1", this bit monitors the overflow status of the internal LCV
counter. An interrupt will not occur unless the LCV_OFIE is set to
"1" in the channel register 0x04h and GIE is set to "1" in the global
register 0x80h.
0 = No Alarm
1 = A line code violation, bipolar violation, or excessive zeros has
occurred
RO
0
D3
Reserved
This Register Bit is Not Used.
D2
AISD
Alarm Indication Signal Detection
The alarm indication signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the AIS
activity. An interrupt will not occur unless the AISIE is set to "1" in
the channel register 0x04h and GIE is set to "1" in the global regis-
ter 0xE0h.
0 = No Alarm
1 = An all ones signal is detected
RO
0
D1
RLOSD
Receiver Loss of Signal Detection
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = An RLOS condition is present
RO
0
D0
QRPD
Quasi Random Pattern Detection
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0x04h and GIE is set to "1" in
the global register 0xE0h.
0 = No Alarm
1 = A QRP is detected
RO
0
N
OTE
:
The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
T
ABLE
27: M
ICROPROCESSOR
R
EGISTER
0
X
05
H
B
IT
D
ESCRIPTION
C
HANNEL
0-7 (0
X
05
H
-0
X
75
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
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