參數(shù)資料
型號(hào)： XRT83VSH38IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PBGA225
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁(yè)數(shù)： 6/76頁(yè)
文件大小： 722K
代理商： XRT83VSH38IB
XRT83VSH38
II
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
T
ABLE
9: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
........................................................................................... 29
4.4 TAOS (TRANSMIT ALL ONES) ...................................................................................................................... 29
F
IGURE
18. TAOS (T
RANSMIT
A
LL
O
NES
) ............................................................................................................................................ 29
4.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 29
4.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 29
F
IGURE
19. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
ATAOS F
UNCTION
..................................................................................................... 30
4.5.2 QRSS/PRBS GENERATION....................................................................................................................................... 30
T
ABLE
10: R
ANDOM
B
IT
S
EQUENCE
P
OLYNOMIALS
................................................................................................................................ 30
4.5.3 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 30
T
ABLE
11: S
HORT
H
AUL
L
INE
B
UILD
O
UT
.............................................................................................................................................. 30
4.5.4 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 30
F
IGURE
20. A
RBITRARY
P
ULSE
S
EGMENT
A
SSIGNMENT
......................................................................................................................... 31
4.6 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 31
4.7 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 31
F
IGURE
21. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
......................................................................................... 31
5.0 T1/E1 APPLICATIONS .........................................................................................................................32
5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 32
5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 32
F
IGURE
22. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
L
OCAL
A
NALOG
L
OOPBACK
................................................................................................ 32
5.1.2 REMOTE LOOPBACK................................................................................................................................................ 32
F
IGURE
23. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
R
EMOTE
L
OOPBACK
.......................................................................................................... 32
5.1.3 DIGITAL LOOPBACK................................................................................................................................................. 33
F
IGURE
24. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
IGITAL
L
OOPBACK
........................................................................................................... 33
5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 33
F
IGURE
25. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
UAL
L
OOPBACK
............................................................................................................... 33
5.2 LINE CARD REDUNDANCY ........................................................................................................................... 34
5.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS.................................................................................................... 34
5.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY.................................................................................. 34
F
IGURE
26. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
................................................ 34
5.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 35
F
IGURE
27. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
.................................................. 35
5.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 36
5.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 36
F
IGURE
28. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
N+1 R
EDUNDANCY
............................................................ 36
5.2.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY................................................................................................... 37
F
IGURE
29. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
N+1 R
EDUNDANCY
.............................................................. 37
5.3 POWER FAILURE PROTECTION .................................................................................................................. 38
5.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 38
5.5 NON-INTRUSIVE MONITORING .................................................................................................................... 38
F
IGURE
30. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
A
N
ON
-I
NTRUSIVE
M
ONITORING
A
PPLICATION
..................................................................... 38
6.0 MICROPROCESSOR INTERFACE ......................................................................................................39
6.1 SERIAL MICROPROCESSOR INTERFACE BLOCK (BGA PACKAGE ONLY) ........................................... 39
F
IGURE
31. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
........................................................................ 39
6.1.1 SERIAL TIMING INFORMATION................................................................................................................................ 39
F
IGURE
32. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
....................................................................................... 39
6.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION ......................................................................................................... 40
6.1.3 ADDR[7:0] (SCLK1 - SCLK8)..................................................................................................................................... 40
6.1.4 R/W (SCLK9)............................................................................................................................................................... 40
6.1.5 DUMMY BITS (SCLK10 - SCLK16)............................................................................................................................ 40
6.1.6 DATA[7:0] (SCLK17 - SCLK24) ................................................................................................................................. 40
6.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 40
F
IGURE
33. T
IMING
D
IAGRAM
FOR
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
....................................................................................... 41
T
ABLE
12: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V± 5%
AND
LOAD
= 10
P
F) ...................................... 41
6.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 42
T
ABLE
13: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
.......................................................................................................... 42
F
IGURE
34. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
........................................................................ 42
6.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 43
T
ABLE
14: XRT83VSH38 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
THAT
EXHIBIT
CONSTANT
ROLES
IN
BOTH
I
NTEL
AND
M
OTOROLA
M
ODES
43
T
ABLE
15: I
NTEL
MODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
........................................................................................................... 43
T
ABLE
16: M
OTOROLA
M
ODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
................................................................................................. 44
6.4 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 45
F
IGURE
35. I
NTEL
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.................................................. 46
T
ABLE
17: I
NTEL
M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
.............................................................................................. 46
6.5 MOTOROLA MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .................................................... 47
F
IGURE
36. M
OTOROLA
68K μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.................................. 48
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