參數(shù)資料
型號： XRT82L38
廠商： Exar Corporation
英文描述： Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）)
中文描述： 八進制E1/T1/J1線收發(fā)器時鐘恢復和抖動衰減器（八的T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器））
文件頁數(shù)： 7/54頁
文件大?。?/td> 356K
代理商： XRT82L38
XRT82L38
OCTAL E1/T1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.5
5
34
RxPOS_5
RData_5
O
O
Receiver 5 Positive Data Output:
In dual-rail mode, this signal is the receive p-rail output data.
Receiver 5 NRZ Data Output:
In single-rail mode, this signal is the receive output data.
35
RxNEG_5
LCV_5
O
O
Receiver 5 Negative Data Output:
In dual-rail mode, this signal is the receive n-rail output data.
Line Code Violation Output:
In single-rail mode, this signal output goes "High" for one receive clock cycle,
to indicate a code violation is detected in the received data. If AMI coding is
selected, every bipolar violation received will cause this pin to go "High".
36
RxClk_5
O
Receiver 5 Clock Output
37
RxLOS_5
O
Receiver 5 Loss of Signal:
This signal is asserted "High" to indicate loss of signal at the receive input.
38
TxClk_5
I
Transmitter 5 Clock Input:
E1 rate at 2.048MHz ± 50ppm. T1 rate at 1.544MHz ± 32ppm.
During normal operation both in Host Mode and Hardware Mode, TxClk is
used for sampling input data at TxPOS/TData and TxNEG, while MCLK is
used as the timing reference for the transmit pulse shaping control. If TxClk is
tied "Low" for more than 16 clock cycles, the respective transmitter is pow-
ered-down with TTIP and TRing placed in high impedance mode. If TxClk is
tied "High" for more than 10μs, TAOS (A continuous all one's AMI signal) will
be transmitted to the line using MCLK as timing reference.
N
OTE
:
Internally pulled
“
High
”
with a 50K
resistor.
39
TxPOS_5
TData_5
I
I
Transmitter 5 Positive Data Input:
In dual-rail mode, this signal is the p-rail input data for transmitter 5.
Transmitter 5 NRZ Data Input:
In single-rail mode, this signal is used as the NRZ input data for transmitter 5.
N
OTE
:
Internally pulled
“
High
”
with a 50K
resistor.
40
TxNEG_5
I
Transmitter 5 Negative Data Input:
In dual-rail mode, this signal is the n-rail data input for transmitter 5.
In single-rail mode, this pin can be left unconnected.
N
OTE
:
Internally pulled
“
High
”
with a 50K
resistor.
41
TxClk_5
I
Transmitter 5 Clock Input:
E1 rate at 2.048MHz ± 50ppm and T1 rate at 1.544MHz ± 32ppm( (see pin 38
description for other usage of this pin.)
N
OTE
:
Internally pulled
“
High
”
with a 50K
resistor.
PIN DESCRIPTION
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
Operating Mode
Normal Mode
Power-down transmitter
TAOS using MCLK as reference
TCLK
Active
Tie Low
Tie High
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