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參數(shù)資料
| 型號： | XRT82L38 |
| 廠商： | Exar Corporation |
| 英文描述： | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）) |
| 中文描述： | 八進制E1/T1/J1線收發(fā)器時鐘恢復和抖動衰減器（八的T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）） |
| 文件頁數(shù)： | 21/54頁 |
| 文件大?。?/td> | 356K |
| 代理商： | XRT82L38 |
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XRT82L38
OCTAL E1/T1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.5
19
RESET OPERATION
The XRT82L38 provides both Hardware and Soft-
ware resets. In Hardware reset, with pin 124 forced to
"0" for more than 10μs, the entire state of the device
including the microprocessor R/W registers are reset.
In Software reset, only the state of the interface is re-
set (the microprocessor registers are not affected).
RECEIVER MODES OF OPERATION
Through the microprocessor interface or in Hardware
Mode, XRT82L38 offers several alternative receive
modes of operation making it flexible for different ap-
plications as dictated by the system requirements.
RECEIVE DATA INVERT MODE
Receive output data by default is active high at Rx-
POS/RDATA and RxNEG/LCV pins. These signals
can be changed to active Low by setting the DATAP
bit in the interface register. In single rail mode
(DataF=1), LCV output also becomes active Low. Da-
ta invert Mode is only available in Host Mode.
F
IGURE
8. A
NALOG
L
OCAL
L
OOP
-B
ACK
SIGNAL
FLOW
JITTER
ATTENUATOR
SELECTED
AND
IN
TRANSMIT
PATH
Rx
Clock &
Data
Recovery
Decoder
TxPOS
TxNEG
TxClk
RxClk
RxPOS
RxNEG
Tx
Encoder
Timing
Control
JA
TTIP
TRing
RTIP
RRing
F
IGURE
9. D
ATA
CHANGES
ON
RISING
EDGE
OF
C
LK
AND
D
ATA
IS
SAMPLED
ON
FALLING
EDGE
F
IGURE
10. D
ATA
CHANGES
ON
FALLING
EDGE
OF
C
LK
AND
IS
SAMPLED
ON
RISING
EDGE
Data Sampled
Clk
Data
Data Sampled
Data Sampled
Clk
Data
Data Sampled
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
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