參數(shù)資料
型號(hào): XRT82L38
廠商: Exar Corporation
英文描述: Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器(帶時(shí)鐘恢復(fù)和振蕩衰減器))
中文描述: 八進(jìn)制E1/T1/J1線收發(fā)器時(shí)鐘恢復(fù)和抖動(dòng)衰減器(八的T1/E1/J1線收發(fā)器(帶時(shí)鐘恢復(fù)和振蕩衰減器))
文件頁(yè)數(shù): 40/54頁(yè)
文件大小: 356K
代理商: XRT82L38
XRT82L38
OCTAL E1/T1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.5
PRELIMINARY
38
T
ABLE
17: C
HANNEL
S
TATUS
B
IT
R
EGISTER
C
HANNEL
S
TATUS
R
EGISTER
P
ARALLEL
P
ORT
A
DDRESS
C
HANNEL
0: 00010
P
ARALLEL
P
ORT
A
DDRESS
C
HANNEL
1: 00101
P
ARALLEL
P
ORT
A
DDRESS
C
HANNEL
2: 01000
P
ARALLEL
P
ORT
A
DDRESS
C
HANNEL
3: 01011
P
ARALLEL
P
ORT
A
DDRESS
C
HANNEL
4: 10010
P
ARALLEL
P
ORT
A
DDRESS
C
HANNEL
5: 10101
P
ARALLEL
P
ORT
A
DDRESS
C
HANNEL
6: 11000
P
ARALLEL
P
ORT
A
DDRESS
C
HANNEL
7: 11011
B
IT
N
O
.
S
YMBOL
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
7
DMOn
Driver Monitor Output: This bit is set to a "1" to indicate current DMO
is detected. Any change in the state of this bit causes an interrupt to
be generated. Reading this register bit does not clear the DMO bit.
R
0
6
LOSn
Loss of Signal: This bit is set to a "1" to indicate current LOS condition
is detected. Any change in the state of this bit causes an interrupt to
be generated. Reading this register bit does not clear the LOS bit.
R
0
5
LCVn
Line Code Violation: This bit is set to a "1" to indicate current LCV
condition is detected. Any change in the state of this bit causes an
interrupt to be generated. Reading this register bit does not clear the
LCV bit.
R
0
4
TCKLn
Transmit Clock Loss: This bit is set to a "1" to indicate current TxClk
clock loss is detected. Any change in the state of this bit causes an
interrupt to be generated. Reading this register bit does not clear the
TCKL bit.
R
0
3
DMOnIS
Driver Monitor Output: This bit is set to a "1" every time the state of
DMO status changes since last read. This bit is cleared by a read
operation.
RUR
0
2
LOSnIS
Latched- Loss of signal: This bit is set to a "1" every time the state of
LOS changes since last read. This bit is cleared by a read operation.
RUR
0
1
LCVnIS
Latched- Line Code Violation: This bit is set to a "1" every time the
state of LCV changes since last read. This bit is cleared by a read
operation.
RUR
0
0
TCLKnIS
Latched-Transmit Clock Loss. This bit is set to a "1" every time the
state of TCKL changes since last read. This bit is cleared by a read
operation.
RUR
0
NOTE: n=channel number 0 to 7.
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