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參數(shù)資料
| 型號(hào)： | XRT82L38 |
| 廠商： | Exar Corporation |
| 英文描述： | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）) |
| 中文描述： | 八進(jìn)制E1/T1/J1線收發(fā)器時(shí)鐘恢復(fù)和抖動(dòng)衰減器（八的T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）） |
| 文件頁數(shù)： | 15/54頁 |
| 文件大?。?/td> | 356K |
| 代理商： | XRT82L38 |
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XRT82L38
OCTAL E1/T1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.5
13
114
TxPOS_3
TData_3
I
I
Transmitter 3 Positive Data Input:
In dual-rail mode, this signal is the p-rail input data for transmitter 3.
Transmitter 3 NRZ Data Input:
In single-rail mode, this signal is used as the NRZ input data for transmitter 3.
N
OTE
:
Internally pulled
“
High
”
with a 50K
resistor.
115
TxNEG_3
I
Transmitter 3 Negative Data Input:
In dual-rail mode, this signal is the n-rail data input for transmitter 3.
In single-rail mode, this pin can be left unconnected.
N
OTE
:
Internally pulled
“
High
”
with a 50K
resistor.
116
RxNEG_3
LCV_3
O
O
Receiver 3 Negative Data Output:
In dual-rail mode, this signal is the receive n-rail output data.
Line Code Violation Output:
In single-rail mode, this signal output goes "High" for one receiveclock cycle
to indicate a code violation is detected in the received data. If AMI coding is
selected, every bipolar violation received will cause this pin to go "High".
117
RxPOS_3
RData_3
O
O
Receiver 3 Positive Data Output:
In dual-rail mode, this signal is the receive p-rail output data.
Receiver 3 NRZ Data Output:
In single-rail mode, this signal is the receive output data.
118
RxClk_3
O
Receiver 3 Clock Output
119
TDI
I
TestData In:
Boundry Scan Test data input
120
TCK
I
Test Clock:
Boundry Scan Clock input
121
TMS
I
Test Mode Select:
Boundry Scan Mode select input
122
TDO
O
Test Data Out:
Boundry Scan Test Data output
123
VDD
****
Digital Positive Supply(3.3V± 5%)
124
Reset
I
Hardware Reset (Active "Low"):
When this pin is tied "Low" for more than 10mS, the device is put in the reset
state. Internally pulled-up with 50K
.
125
GND
****
Digital Ground
126
127
128
129
130
131
132
133
D[7]
LOOPEN_7
D[6] / LOOPEN_6
D[5] / LOOPEN_5
D[4] / LOOPEN_4
D[3] / LOOPEN_3
D[2] / LOOPEN_2
D[1] / LOOPEN_1
D[0] / LOOPEN_0
I/O
I
Host Mode, Data Bus[7]:
Microprocessor read/write data bus.
Hardware Mode, Loop-back Enable Channel 7:
Connect this pin "High" to enable channel 7 loop-back operation. Remote or
local loop-back is determined by pin 58 setting. Digital Loop-back is not sup-
ported in Hardware Mode.
Host Mode, Data Bus[6] / Hardware Mode, Loop-back Enable Channel 6
Host Mode, Data Bus[5] / Hardware Mode, Loop-back Enable Channel 5
Host Mode, Data Bus[4] / Hardware Mode, Loop-back Enable Channel 4
Host Mode, Data Bus[3] / Hardware Mode, Loop-back Enable Channel 3
Host Mode, Data Bus[2] / Hardware Mode, Loop-back Enable Channel 2
Host Mode, Data Bus[1] / Hardware Mode, Loop-back Enable Channel 1
Host Mode, Data Bus[0] / Hardware Mode, Loop-back Enable Channel 0
134
VDD
****
Analog Positive Supply(3.3V± 5%)
135
RxClk_2
O
Receiver 2 Clock Output
PIN DESCRIPTION
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
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