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參數(shù)資料
| 型號： | XRT82L38 |
| 廠商： | Exar Corporation |
| 英文描述： | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）) |
| 中文描述： | 八進(jìn)制E1/T1/J1線收發(fā)器時鐘恢復(fù)和抖動衰減器（八的T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）） |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 356K |
| 代理商： | XRT82L38 |
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XRT82L38
OCTAL E1/T1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.5
PRELIMINARY
20
RxClk Clock Sampling Edge
The sampling edge of the RxClk output can be
changed through control bit RClkE within the inter-
face register for receive output data re-timing. With
RClkE=1, data is validated on the rising edge of Rx-
Clk and with RClkE=0, receive data is validated on
the falling edge of RxClk. In Hardware Mode, the
state of pin 33 (ClkE) controls the rising or falling
edge of RxClk for data re-timing.
TRANSMIT CLOCK SAMPLING EDGE
Transmit data at TxPOS/TDATA or TxNEG is clocked
serially into the device using TxClk. With the interface
register bit 4 (TClk=1), input data is sampled on the
rising edge of TxClk. The sampling edge is inverted
when TxClk= 0. In Hardware Mode, the state of pin
33 (ClkE) controls the sampling edge of both TxClk
and RxClk.
SINGLE RAIL, DUAL RAIL
Transmit data format can be in dual-rail (SR/DR=1) or
single-rail modes (SR/DR=0). In Hardware Mode, du-
al or single-rail format is determined by the state of
pin 8. For single-rail mode operation, NRZ data can
be applied to TxPOS/TDATA with TxClk, while TxNEG
input is left unconnected. The transmitter converts
NRZ input data into differential signal for transmission
to the line using low impedance output drivers.
TRANSMIT ALL ONES (TAOS)
In the Host Mode, individual channels can be pro-
grammed to transmit an all
“
Ones
”
AMI signal by set-
ting the per channel bit control TAOS=1. In this mode,
input data at TxPOS/TDATA and TxNEG are ignored.
In Host Mode, reference clock for TAOS is TxClk. If
TxClk is not available, MCLK is used for transmission.
In Hardware Mode, if TxClk is not present and High
for more than 10μs, TAOS is transmitted using MCLK
as a reference. Remote Loop-Back has priority over
TAOS request.
HDB3/B8ZS/AMI ENCODER
The encoder is only available in single-rail mode (SR/
DR=1) in Host Mode, or pin 8 set High in Hardware
Mode. In an E1 system, if interface register
CODES=0, HDB3 encoding is selected. Input data
applied to TxPOS/TDATA which contains more than
four consecutive zeros will be removed and replaced
by
“
000V
”
or
“
B00V
”
, where "B
”
indicates a pulse con-
forming with bipolar rule and "V" represents a pulse
violating the rule. In a T1 system, input data with
more than 8 consecutive zeros will be removed and
replaced using B8ZS encoding rule. An example of
Bipolar with 8 Zero Substitution (B8ZS) encoding
scheme is shown in Table 1. With register
CODES=1, AMI coding is selected for both E1 or T1
modes. In Hardware Mode, HDB3, B8ZS or AMI cod-
ing selection is determined by the state of pin 10.
TRANSMIT PULSE SHAPER
The transmit pulse shaper uses high a speed clock
derived from MCLK to synthesize the shape and
width of the transmitted pulse applied to TTIP and
TRING. The internal high speed timing generator
eliminates the need for a tightly controlled transmit
clock TxClk duty cycle. In a T1 system, three control
bits (ECC, ECB and ECA) are available in the Host
Mode, for every channel to select 5 different cable
length pulse settings to meet DSX-1 pulse template.
Table 2 summaries the function of these control bits.
In Hardware Mode, all 4 transmit channels share the
same pulse synthesizer control settings.
DRIVER MONITOR
The driver monitor circuit is used for detecting trans-
mit driver failure by monitoring the activity at TTIP
and TRING. Driver failure may be caused by a short-
circuit in the primary of the transformer or system
problems at the input.
In the Host Mode, when the driver monitor detects no
transitions at TTIP and TRING for more than 128
clock cycles, the DMO bit in the interface register is
set and results in an interrupt (INT) to be generated.
Driver monitor function is not supported in Hardware
Mode.
TxPOS/TDATA and TxNEG Polarity
In HOST Mode, transmit data at TxPOS/TDATA and
TxNEG can be configured for active Low or active
High operation, by controlling the state of the DATAP
bit in the interface register. Writing a "0" to this bit se-
lects active High data and a "1" selects active Low
data. This control bit also selects receive output data
polarity (see Receive Data Invert Mode description).
This feature is not supported in Hardware Mode.
TRANSMIT OFF CONTROL
Each transmit channel of the line interface can be
shut down by writing a "1" to TxOFF in the channel
control interface register. In the
“
Transmitter off
”
mode, the entire transmitter is disabled and the out-
puts at TTIP and TRING are placed in a high imped-
ance state. If MCLK is missing, then all transmitters
will be powered down and the outputs are tri-stated.
G.772 PROTECTED MONITORING
XRT82L38 consists of eight identical transmit and re-
ceive channel for T1 or E1 system. In applications
where only seven channel of the eight line interfaces
are used, the eighth receive and transmit channel can
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